FPGA Control Section for Electronic Endoscope
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Solution Overview
Problem
Conventional electronic endoscopic apparatuses face inefficiencies in circuit usage and reliability due to the need for multiple CPUs and peripheral circuits for different operation modes, leading to increased substrate size and the risk of short circuits, and the challenge of using watch dog timers with shorter timeout periods causing repetitive restarts during CPU startup.
Innovation Solution
The apparatus includes a control section with a switching request detecting section, a dummy pulse generating section, and an abnormality monitoring system that dynamically changes internal configurations based on detected requests, using a watch dog timer with a shorter timeout period to prevent repetitive restarts by generating a dummy pulse signal during startup and detecting completion of initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple CPUs and peripheral circuits are prepared for each operation mode, then the reliability and safety level are improved through mode checking, but the substrate area increases and circuit usage efficiency decreases
Solution Approach 1:
The patent merges multiple operation modes into a single CPU and peripheral circuit by implementing mode switching capability. The control section integrates normal mode and safety mode functionalities in one unified circuit, using a mode switching section to activate appropriate functions based on the current operation mode, thereby reducing substrate area while maintaining reliability through mode-based safety checking
Solution Approach 2:
The patent makes the single CPU and peripheral circuit universal by enabling them to perform multiple operation modes. The control section is designed to handle both normal medical treatment operations and safety mode operations using the same hardware resources, improving circuit usage efficiency while maintaining the ability to check and switch between modes for safety
2Reliability
If multiple CPUs and peripheral circuits are prepared for each operation mode, then the safety level is improved through mode checking, but the circuit usage efficiency decreases
Solution Approach 1:
The patent combines multiple operation modes into a single shared CPU and peripheral circuit system. The control section integrates functionalities for both normal mode and safety mode in one unified circuit, allowing the same hardware resources to be reused across different operation modes, thereby improving circuit usage efficiency while maintaining safety through mode-based checking
Solution Approach 2:
The patent introduces dynamic mode switching capability to the control section. The operation mode can be switched between normal mode and safety mode based on external mode instructions or apparatus state, allowing the single CPU and peripheral circuit to adaptively change their functional configuration, improving resource utilization while maintaining reliability
3Speed
If a watch dog timer with shorter timeout period is used, then the responsiveness to CPU runaway is improved, but repetitive restarts occur during CPU startup
Solution Approach 1:
The patent applies preliminary action by having the watch dog timer ignore reset signals during the CPU startup period. The system pre-determines a startup time window and temporarily suspends the watch dog timer's reset function during this period, allowing the CPU to complete its initialization without being prematurely reset, while still maintaining quick responsiveness to runaways after startup
Data Source
AI summary
An electronic endoscopic apparatus of the present invention can improve the usage efficiency of a circuit of a control section therein and can improve the reliability of operations of the circuit. The electronic endoscopic apparatus is an electronic endoscopic apparatus having multiple operation modes to be executed exclusively, the apparatus internally including an FPGA 1 that internally includes a CPU 10 and peripheral circuits and controls the execution of the operation modes and a switching request detecting section that detects a request for switching to the operation mode to be executed, wherein the internal configuration of the FPGA 1 is changed based on the detection result by the switching request detecting section.