FPGA Soft Error Recovery via Busy Path State
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Solution Overview
Problem
The existing storage system recovery from soft errors in FPGAs is inefficient and time-consuming, requiring operator intervention and unnecessary hardware exchanges, as it disables the path between the host and storage device during recovery, leading to complex and slow recovery processes.
Innovation Solution
A storage control apparatus with a detection unit for soft errors in programmable logic circuits, a communication control unit to change the communication path state to busy, and a recovery processing unit that performs reconfiguration without hard resets, allowing for efficient recovery of the FPGA without disabling the host path and reducing the need for hardware exchanges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard reset is performed to recover soft error in FPGA, then the FPGA is recovered from soft error state, but the communication path between host and storage device is disabled and recovery time is extended
Solution Approach 1:
The system performs preliminary detection of soft errors in the FPGA configuration RAM and changes the communication path state to busy before actual recovery is needed. This allows the system to prepare for recovery without immediately disabling the communication path, thereby reducing recovery time while maintaining reliability.
Solution Approach 2:
The communication control unit acts as an intermediary that manages the state of the communication path. By controlling the path state to be busy during soft error recovery without completely disabling it, the system maintains connectivity while performing recovery operations, thus reducing downtime.
2Reliability
If hard reset is performed to recover soft error in FPGA, then the FPGA is recovered from soft error state, but operator intervention and hardware exchange operations are required
Solution Approach 1:
The system implements self-service recovery by automatically detecting soft errors in the FPGA configuration RAM and performing recovery operations without requiring operator intervention. The storage control apparatus autonomously manages the recovery process, eliminating the need for hardware exchange operations and reducing operational complexity.
Solution Approach 2:
The detection unit continuously monitors the FPGA configuration RAM for soft errors and provides feedback to the control unit. This feedback mechanism enables automatic recovery operations based on real-time error detection, eliminating the need for manual intervention and simplifying the recovery process.
3Reliability
If path disconnection is recognized during soft error recovery, then the failure notification is issued, but unnecessary failure notifications are generated and hardware exchange is triggered
Solution Approach 1:
The system changes the communication path state to busy in advance when a soft error is detected, before any failure notification is issued. This preliminary action prevents the system from recognizing the path as disconnected, thereby avoiding false failure notifications and unnecessary hardware exchange operations while maintaining accurate error detection.
Data Source
AI summary
A storage control apparatus includes a detection unit that detects a soft error of a memory for setting information included in a programmable logic circuit, when the soft error is detected, a communication control unit that changes a state of a communication path between the communication device and an upper device to a busy state, and a recovery processing unit that performs recovery processing of the memory for setting information of the programmable logic circuit, thereby efficiently resolving a soft error of the programmable logic circuit.