FPGA Ethernet Packet Processing with iNOC Load Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional FPGAs face challenges in handling high-throughput Ethernet networking due to lower operating frequencies of user logic, leading to congestion and difficulty in meeting timing requirements, with networking IP cores located at the boundary and requiring complex data path design.
Innovation Solution
Implementing an internal network on chip (iNOC) within the FPGA core to efficiently load-balance Ethernet traffic, allowing data movement without user logic intervention, supporting various Ethernet speeds, and enabling packet rearrangement for efficient data path utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If packet processing is performed using conventional hardware circuits, then processing speed is sufficient, but reconfigurability and adaptability to new protocols are poor
Solution Approach 1:
The packet processing system is divided into separate functional modules: a reconfigurable packet processor implemented with programmable logic, and a dedicated hardware flow controller. This segmentation allows the programmable logic to be reconfigured for different protocols while the hardware flow controller maintains fixed, optimized packet handling functions, thus achieving reconfigurability without requiring complete system redesign.
Solution Approach 2:
A software bridge is introduced as an intermediary component between the packet processor and the flow controller. This software bridge enables communication and coordination between the reconfigurable programmable logic and the fixed hardware circuitry, allowing flexible protocol implementation while maintaining the performance benefits of dedicated hardware for packet processing.
2Adaptability or versatility
If packet processing is performed using programmable logic devices, then reconfigurability is improved, but processing speed and resource utilization are reduced
Solution Approach 1:
The system segments packet processing into two paths: high-speed fixed hardware processing for standard packet handling operations, and reconfigurable programmable logic processing only when needed for protocol-specific requirements. This allows the system to maintain high processing speeds for common operations while providing reconfigurability for specialized tasks.
Solution Approach 2:
Rather than making the entire packet processing system programmable (which would reduce overall speed), the invention applies programmable logic only to the extent necessary for protocol reconfiguration, leaving the majority of packet processing functions implemented in fixed hardware that operates at full speed.
3Speed
If dedicated hardware circuits are used for packet processing, then processing speed is high, but flexibility to handle different protocols is limited
Solution Approach 1:
The flow controller is designed with multi-functionality, serving both as a hardware controller for packet processing and as a software interface for protocol configuration. This universal design allows the same hardware component to provide fixed high-speed packet handling while also enabling flexible protocol adaptation through software control of the programmable logic.
Solution Approach 2:
The software bridge acts as an intermediary that enables flexible protocol handling by mediating between the reconfigurable packet processor and the fixed hardware flow controller. This allows different protocols to be implemented through software configuration while maintaining the high-speed processing capabilities of the dedicated hardware circuitry.
4Device complexity
If existing hardware resources are utilized, then device complexity is reduced, but functionality for advanced packet processing is insufficient
Solution Approach 1:
The invention merges existing hardware packet processing resources with reconfigurable programmable logic in a unified system. The hardware flow controller and packet processor are combined with programmable logic devices, allowing the system to leverage existing hardware capabilities while adding reconfigurable functionality through the programmable components.
Solution Approach 2:
The system introduces dynamic reconfigurability through programmable logic that can be reconfigured based on protocol requirements, while the hardware components remain static. This dynamic aspect allows the system to adapt its processing functionality without changing the underlying hardware architecture, thus maintaining hardware simplicity while enhancing processing capabilities.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising iNOC rows and iNOC columns; clusters coupled to the iNOC, each cluster comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. The Ethernet controller is configurable to operate in packet mode where each complete inbound Ethernet packet is sent from the Ethernet controller to one of the NAPs via the iNOC, wherein two or more NAPs are configurable to receive the complete inbound Ethernet packets from the Ethernet controller.