External PLL FPGA Clock Alignment Without Domain Crossing Latency
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face a technical challenge in synchronizing receiver and transmitter clock signals, which introduces unwanted latency and delays in processing, particularly in high-frequency applications like high-frequency trading where microsecond accuracy is crucial.
Innovation Solution
A field programmable gate array system with an external phase controller that provides phase matching between receiver and transmitter clocks without using clock domain crossing circuits, utilizing a deserializer, serializer, phase detector, and adjustable oscillator to align the phases of the clock signals, thereby eliminating unnecessary delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock domain crossing circuits are used to synchronize receiver and transmitter clocks in FPGA, then phase synchronization is achieved, but processing latency increases
Solution Approach 1:
The patent extracts the phase synchronization function from the FPGA's internal clock domain crossing circuits and relocates it to an external phase controller device. This separation allows the FPGA to process data without internal synchronization delays while the external device independently manages clock phase alignment, thus achieving phase synchronization without increasing processing latency within the FPGA.
Solution Approach 2:
The patent introduces an external phase controller as an intermediary device between the receiver and transmitter clock domains. This mediator compares the phases of receiver and transmitter clocks and generates correction signals to align them, enabling phase synchronization without requiring clock domain crossing circuits within the FPGA that would introduce latency.
2Reliability
If internal phase-locked loop is used within FPGA for clock synchronization, then clock alignment is achieved, but processing speed decreases
Solution Approach 1:
The patent extracts the phase-locked loop functionality from the FPGA's internal architecture and places it in an external phase controller. This allows the FPGA to operate at full speed without internal clock synchronization overhead, while the external PLL handles clock alignment independently, thus maintaining high processing speed while achieving reliable clock alignment.
3Reliability
If clock synchronization circuits are integrated in FPGA, then phase matching is achieved, but device complexity increases
Solution Approach 1:
The patent extracts the complex phase matching circuitry from the FPGA and relocates it to an external phase controller device. This separation simplifies the FPGA's internal architecture by removing synchronization circuits, while the external device assumes the complexity of implementing phase matching functionality, thus achieving phase matching without increasing FPGA device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables sub-microsecond processing throughput with minimal latency, supporting data rates of 10-120 Gbps, ensuring accurate timestamping and efficient data processing in high-frequency trading applications.
Implementation Method 1
a phase detector operationally connected to the first clock output pin and the second clock output pin of the second interface of the field programmable gate array, and wherein the phase detector is configured to compare the third phase of the receiver side clock signal to the fifth phase of the transmitter side clock signal and to generate a phase difference indicator signal based on a difference between the third phase of the receiver side clock signal and the fifth phase of the transmitter side clock signal
Implementation Method 2
an adjustable oscillator operationally connected to the phase controller and configured to receive the adjustment information as well as operationally connected to the second reference clock pin of the first interface of the field programmable gate array, wherein the adjustable oscillator is configured to generate the second clock signal including the second frequency and the second phase based on the adjustment information
Data Source
AI summary
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.