FPGA FBLMS Processing with Block Floating-Point and Dynamic Truncation
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Solution Overview
Problem
Traditional FPGA devices face challenges in implementing the FBLMS algorithm due to conflicts between performance, speed, and resource usage, particularly in handling high-precision floating-point operations and ensuring accurate timing control for complex algorithms like FBLMS.
Innovation Solution
The implementation of an FPGA device for the FBLMS algorithm using block floating-point data formats, which includes modules for input caching and conversion, filtering, error calculation, weight adjustment, and updating, employing techniques like dynamic truncation and modular design to manage resource usage and timing control effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fixed-point system is used in FPGA for FBLMS algorithm, then hardware resource usage is reduced, but data accuracy and dynamic range are insufficient
Solution Approach 1:
The patent transforms the fixed-point data representation into block floating-point format, changing the numerical parameter system. This allows the FPGA to handle a wider dynamic range and maintain higher precision for weight vectors during convergence, while still using integer arithmetic operations that are efficient for hardware implementation.
Solution Approach 2:
The patent segments the floating-point number into block exponent and mantissa components. By processing these segments separately using integer arithmetic, the system achieves floating-point precision without requiring complex hardware multipliers and adders, thus reducing hardware resource usage while maintaining data accuracy.
2Measurement precision
If high-precision floating point operation is implemented in FPGA, then data accuracy is improved, but hardware resource consumption increases significantly
Solution Approach 1:
The patent substitutes complex floating-point arithmetic operations with integer arithmetic operations. By representing floating-point numbers as block floating-point format and using integer multiplication and addition, the system avoids the need for complex hardware floating-point units, significantly reducing hardware resource consumption while maintaining precision.
3Reliability
If complex timing control is implemented for accurate data alignment in FBLMS, then algorithm performance is improved, but device complexity increases
Solution Approach 1:
The patent employs periodic block-based processing where data is divided into blocks and processed in regular intervals. This periodic structure simplifies timing control by establishing predictable patterns for data alignment and processing, reducing the complexity of timing synchronization while maintaining accurate data alignment across different processing stages.
4Measurement precision
If block floating point format is used with dynamic truncation, then finite word-length effect is reduced, but processing complexity increases
Solution Approach 1:
The patent applies dynamic truncation that retains only the necessary significant bits for each calculation stage. By performing partial action (truncating less significant bits that have minimal impact on the result), the system reduces the finite word-length effect and maintains algorithm performance while simplifying the processing requirements compared to maintaining full precision throughout.
Data Source
AI summary
Disclosed in the present disclosure is an FPGA implementation device and method for an FBLMS algorithm based on block floating point. The method includes: blocking, caching, and reassembling a reference signal, by an input caching and converting module, converting into a block floating point system and performing FFT; filtering, by a filtering module, in a frequency domain and performing dynamic truncation; caching, by an error calculating and output caching module, a target signal on a block basis, converting into a block floating point system, subtracting an output result output from the filtering module from the converted target signal to obtain an error signal, converting the error signal into a fixed point system to obtain a final cancellation result; obtaining, by a weight adjustment amount calculating module and a weight updating and storing module, an adjustment amount of a frequency domain block weight and updating the frequency domain block weight.