FPGA Folding Grid Architecture for Energy-Efficient Max Flow Processing
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Solution Overview
Problem
Current technologies, including advanced GPU platforms, face challenges in efficiently processing large grid graphs due to memory access delays and high energy consumption, even with parallel acceleration methods like JF-cut and RipplePush, as they require significant FPGA resources and struggle with data dependency and cross-layer data transmission.
Innovation Solution
The method involves preprocessing a large grid graph into a folding grid data structure, allowing for a multi-layer small grid graph that can be processed by a small-sized processor array, utilizing a disordered parallel execution technology with FIFO queues to enable simultaneous processing across layers, reducing data movement and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a one-to-one correspondence architecture between computing nodes and grid graph nodes is used, then parallel performance is improved, but FPGA resource consumption increases significantly
Solution Approach 1:
The patent segments the grid graph nodes into multiple groups and maps them to a smaller array of computing nodes. Each computing node processes multiple grid graph nodes through a systematic mapping scheme, reducing the number of required computing nodes from H×W to approximately H×W/4 while maintaining parallel processing capability.
Solution Approach 2:
The patent introduces a third dimension (layer index) to the mapping relationship. Instead of direct one-to-one correspondence, nodes are mapped through intermediate layer indices, enabling multiple grid nodes to share computing resources across different layers while maintaining systematic access patterns.
2Adaptability or versatility
If universal computing platforms (GPU) are used for acceleration, then programming flexibility is improved, but memory access delay and energy consumption increase
Solution Approach 1:
The patent replaces the memory-access-intensive GPU architecture with an FPGA architecture that computes results directly in hardware registers. By eliminating the need for frequent DRAM accesses and using combinational logic circuits, the system achieves the same computational task with significantly lower energy consumption while maintaining flexibility through configurable mapping parameters.
3Reliability
If data dependency between adjacent nodes is addressed through architecture, then computation accuracy is improved, but data transmission overhead increases
Solution Approach 1:
The patent designs the mapping such that all computing nodes operate at the same computational level and process data from their local buffers simultaneously. This equipotential approach eliminates hierarchical data transmission delays and ensures consistent processing across the entire grid graph, reducing overall transmission overhead while maintaining computational accuracy.
Data Source
AI summary
A disordered parallel maximum flow/minimum cut method implemented by an energy-efficient field-programmable gate array (FPGA) folds a single-layer large two-dimensional grid graph into a multi-layer small grid graph. The method enables a folding grid architecture to store and process a grid graph that is much larger than a processor array in size. The folding grid architecture endows a two-dimensional processor array with a degree of freedom in a vertical direction, such that the two-dimensional processor array can leverage a potential for parallel performance of the folding grid architecture based on the degree of freedom in the vertical direction. The folding grid architecture enables a small-sized processor array to have an ability to process a grid graph that is much larger than the small-sized processor array in size. In addition, based on axial symmetry of folding, the folding grid architecture can greatly reduce cross-boundary transmission of data in the processor array.