FPGA Forwarding Plane with Unified Memory for Parallel Networking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Heterogeneous computing systems using single field programmable gate array (FPGA) devices are limited by the size of the programmable logic fabric and finite resources, which restricts performance for parallel tasks requiring larger memory and faster execution, while GPU-based systems are limited by the number of GPUs and proprietary interconnects.
Innovation Solution
Configuring an array of multiple FPGA devices with a host processor and interconnect logic to enable parallel execution of source code, utilizing a topology and partitioning module to optimize resource utilization and expand global memory, allowing for unified address spaces and enhanced computational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single FPGA device is used for heterogeneous computing, then the system is simpler to manage, but the computational performance and memory capacity are limited by the size of the programmable logic fabric
Solution Approach 1:
The system divides the computational task into parallel segments that can be executed across multiple FPGA devices. The parallelized portion of source code is partitioned among multiple FPGAs, each processing a subset of computations simultaneously, thereby achieving higher overall productivity while maintaining manageable complexity through modular organization
Solution Approach 2:
Multiple FPGA devices are merged into a unified parallel processing system with a common global memory address space. The FPGAs work together as a coordinated ensemble, combining their computational resources to achieve performance that exceeds the sum of individual devices while presenting a unified interface to the host processor
2Quantity of substance
If multiple FPGA devices are configured in an array, then global memory capacity and parallel processing capability are expanded, but the system complexity and interconnect requirements increase
Solution Approach 1:
The array interconnect is designed as a universal communication infrastructure that handles multiple functions: data transfer between FPGAs, memory access coordination, and synchronization. This multi-functional interconnect reduces overall system complexity by consolidating multiple communication paths into a single versatile network
Solution Approach 2:
The array interconnect acts as an intermediary layer between the host processor and multiple FPGA devices, and between FPGAs themselves. It mediates memory access requests, manages data flow, and coordinates communication, thereby simplifying the interface requirements for each individual FPGA while enabling expanded global memory capacity
3Speed
If source code is partitioned among multiple FPGA devices, then parallel execution speed is improved, but the difficulty of code distribution and resource allocation increases
Solution Approach 1:
The code partitioning system is designed to be dynamic and adaptive, automatically adjusting the distribution of computational tasks across FPGAs based on available resources and performance requirements. The parallelized source code can be reconfigured without manual intervention, reducing the complexity of code distribution while maintaining optimal execution speed
Solution Approach 2:
The system employs self-service mechanisms where the parallel execution environment automatically manages code partitioning and resource allocation. The FPGAs and interconnect system self-coordinate to distribute and execute partitioned code segments, eliminating the need for complex manual code distribution while achieving high execution speed through parallel processing
Data Source
AI summary
A forwarding plane comprising a scalable array of field programmable gate array (FPGA) devices, a memory bank, FPGA data and transport network ports, and an array interconnect. The scalable array is configured to execute a networking application source code partitioned as computing elements executed by the FPGA devices with a uniform global memory address space. The memory bank includes an allocated portion of the FPGA devices addressable by the address space. The ports are coupled to data networks and include ingress ports configured to receive traffic and egress ports configured to transmit traffic. The array interconnect is configured to forward the traffic from the ingress ports to the egress ports, choose cell sizes of data cells that encapsulate payload data units of the traffic, control latency between the FPGA devices based on the chosen cell sizes; and enable utilization of the memory bank for buffering of the traffic.