FPGA Configuration Frame Compression Using Don't-Care Bit Merging
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Solution Overview
Problem
Conventional programmable logic devices require large external memory and long loading times for configuration bitstreams, and existing compression algorithms do not effectively reduce data size without additional decompression hardware.
Innovation Solution
Identifying and merging 'don't care' bits in configuration frames, using a graph-based approach to combine identical frames and store them using a multi-frame write process, which reduces the size of the configuration data without requiring additional decompression hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional configuration bitstreams are used without compression, then the device can be configured correctly, but large external memory is required and loading time is long
Solution Approach 1:
The patent merges identical configuration frames by identifying frames that produce the same device functionality (using don't care bit masking) and combining them into single stored representations. This reduces the total number of frames that need to be loaded from external memory, directly decreasing both configuration data size and loading time without requiring decompression hardware.
Solution Approach 2:
The patent changes the representation parameters of configuration data by introducing don't care bit masking, where certain bits are marked as irrelevant to functionality. This allows frames to be considered equivalent based on functional equivalence rather than exact bit matching, enabling compression while maintaining correct device configuration.
2Quantity of substance
If LZ compression algorithm is used, then configuration data size is reduced by factor of two, but additional decompression logic is required in the FPGA
Solution Approach 1:
The patent makes the configuration system self-service by using the existing multi-frame write capability of the FPGA's configuration logic to handle the decompression process. The compressed frames are loaded and automatically expanded using the device's own configuration infrastructure, eliminating the need for separate decompression logic while achieving compression ratios exceeding 2:1.
3Productivity
If multi-frame write capability is used, then frames can be written to multiple addresses, but compression is only effective when complete frames are identical
Solution Approach 1:
The patent changes the comparison parameter from exact bit matching to functional equivalence matching using don't care bit masks. This allows frames that differ only in non-critical bits to be identified as equivalent and compressed together, significantly increasing compression effectiveness while still utilizing the multi-frame write capability for efficient loading.
Data Source
AI summary
Method and apparatus for processing configuration data for a programmable logic device is described. The configuration data includes a sequence of frames. In one example, bits in the sequence of frames are identified as “don't care” bits that do not affect the functionality of a design implemented in the programmable logic device. Frames in the sequence of frames are compared to identify at least one set of identical frames, where the “don't care” bits are deemed to result in matches. Each of the at least one set of identical frames is merged to produce a respective at least one merged frame. Each of the at least one merged frame is associated with a plurality of configuration memory addresses in the programmable logic device. Each of the at least one merged frame may be loaded into configuration memory of the programmable logic device using a multi-frame write process.