Gated Clock Buffers for FPGA Dynamic Power Reduction
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Solution Overview
Problem
Current programmable logic device (PLD) designs, such as FPGAs and CPLDs, face challenges in reducing dynamic power consumption due to the high demand on routing area and buffer resources caused by clock enable lines, which are often heavily loaded and require additional power.
Innovation Solution
The method involves modifying the FPGA netlist to efficiently distribute gated clock signals by identifying groups of synchronous elements with common clock and clock enable signals, adding gated clock buffers, and removing clock enable signals to conserve dynamic power, while ensuring power savings through a power analysis process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock enable lines are used to save dynamic power in individual clocked elements, then dynamic power consumption at the element level is reduced, but routing area and buffer resources are heavily consumed
Solution Approach 1:
The patent merges the clock enable function into the clock distribution network itself by inserting gated clock buffers at strategic points in the clock tree. Instead of routing individual clock enable signals to each clocked element, the enable signal is combined with the clock signal in the distribution network, allowing multiple elements to share the same gated clock buffer and thus reducing routing area requirements.
Solution Approach 2:
The patent introduces gated clock buffers as intermediary elements in the clock distribution network. These buffers act as mediators that receive both clock and enable signals, perform the gating function, and distribute the gated clock signal to multiple clocked elements. This intermediary approach consolidates the gating function away from individual elements, reducing the need for dedicated enable routing to each element.
2Loss of energy
If clock enable lines are routed to many clocked elements, then individual elements can be powered down selectively, but buffer resources are heavily consumed
Solution Approach 1:
The patent merges multiple clock enable signals or consolidates the enable function into shared gated clock buffers that serve multiple clocked elements. By combining the gating function at the buffer level rather than at each element level, the total number of buffers required is significantly reduced while maintaining selective power-down capability.
Solution Approach 2:
The gated clock buffers serve multiple functions: they distribute the clock signal, implement the gating function to save power, and can serve multiple clocked elements simultaneously. This multi-functionality reduces the overall buffer resource consumption compared to having dedicated enable routing and buffering at each element.
3Ease of operation
If heavily loaded clock enable lines are used, then selective clock disabling is achieved, but additional power is consumed by the buffers
Solution Approach 1:
The patent extracts the clock enable function from the individual element level and relocates it to the clock distribution network level. By taking out the gating function from each element's input stage and placing it in shared buffers within the clock tree, the solution reduces the number of heavily loaded enable lines and the associated buffer power consumption while preserving selective disabling capability.
Solution Approach 2:
The gated clock buffers serve as intermediaries that handle the gating function centrally. Instead of having many buffers drive heavily loaded enable lines to individual elements, the intermediary buffers in the clock distribution network handle the gating for multiple elements, reducing overall buffer power consumption while maintaining operational control.
Data Source
AI summary
Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.