Formal Gated Clock Conversion for FPGA Synthesis
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Solution Overview
Problem
Field Programmable Gate Array (FPGA) synthesis for ASIC prototyping faces challenges in minimizing the number of unique clock signals, as hardware designers often create numerous unique clock signals due to embedded clock gating, which is not optimized for FPGA resources.
Innovation Solution
The method involves formal gated clock conversion, where a gated clock function is analyzed to separate enable functions from clock functions, allowing the derivation of a primary clock signal and enable signals, which are then attached to dedicated pins, reducing the number of unique clock signals through structural and functional analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardware designers create numerous unique clock signals with embedded clock gating for ASIC designs, then the design can achieve fine-grained control and power management, but the number of unique clock signals increases beyond FPGA capabilities
Solution Approach 1:
The patent segments the clock control function by separating the clock signal generation from the enable control. Instead of creating multiple unique clock signals, the system uses a single primary clock signal combined with separate enable signals to achieve fine-grained control. This segmentation allows the clock and enable functions to be independently optimized and managed.
Solution Approach 2:
The patent extracts the enable function from the gated clock function. By taking out the enable control logic from the clock generation, the system can use a single primary clock signal and attach enable signals to dedicated enable pins of target registers. This extraction reduces the number of unique clock signals while preserving the fine-grained control capability through separate enable mechanisms.
2Device complexity
If FPGA synthesis supports a limited number of unique clock signals, then the device complexity is reduced and resources are optimized, but the ability to support complex clocking schemes is limited
Solution Approach 1:
The patent implements a universal clocking approach where a single primary clock signal serves multiple functions through combination with enable signals. The same primary clock can be used to clock different registers and memory elements, with the enable signals providing the necessary control for each component. This multi-functionality allows the limited FPGA clock resources to support complex clocking schemes.
Solution Approach 2:
The patent introduces enable signals as intermediary components between the primary clock signal and the target registers. These enable signals act as mediators that control when the clock signal is active for each register, allowing fine-grained control without requiring multiple unique clock signals. The enable signals bridge the gap between the limited clock resources and the complex clocking requirements.
3Quantity of substance
If gated clock conversion separates enable functions from clock functions, then the number of unique clock signals is minimized, but the complexity of the conversion process increases
Solution Approach 1:
The patent performs preliminary analysis of the gated clock functions during the synthesis process. By analyzing the enable functions and clock functions separately in advance, the system can identify opportunities for optimization and automatically generate the appropriate enable signals and clock assignments. This preliminary action simplifies the overall conversion process by planning the optimization strategy before implementation.
Data Source
AI summary
Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.