FPGA Clock Domain Synchronization via GCD Pre-Alignment
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Solution Overview
Problem
Modern PLL-based ASIC/FPGAs face challenges in achieving deterministic phase alignment due to the loss of lock in the PLL controlling the serializer when the clock is gated, making it difficult to synchronize multiple devices across arbitrary clock domains.
Innovation Solution
The solution involves using DDS technology, software, and FPGA IP to create greatest common divisor (GCD) clock domains and soft train digital interfaces for pre-synchronization. This includes determining the GCD of all related clock periods, programming DDS outputs to provide reference clocks to PLLs, and recreating the GCD inside FPGAs through training sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock is gated to the serializer in modern PLL-based ASIC/FPGAs, then power consumption is reduced, but the PLL loses lock and deterministic phase alignment is destroyed
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing arbitrary clock domains to a common GCD clock domain before serialization. This is achieved by: (1) determining the greatest common divisor (GCD) of all related clock periods, (2) programming DDS outputs to provide reference clocks to PLLs at the target frequency, and (3) recreating the GCD inside FPGAs through training sequences. This preliminary synchronization ensures that when clocks are later gated for power saving, the PLLs remain locked and deterministic phase alignment is maintained.
2Measurement precision
If external clocks are gated and ungated for synchronization, then deterministic phase alignment can be achieved in traditional systems, but this approach is unviable with modern PLL-based systems as the PLL loses lock
Solution Approach 1:
The patent applies parameter changes by transforming the clock domain synchronization approach from simple clock gating to a multi-stage process involving GCD calculation, DDS-based reference clock generation, and training sequences. The key parameter change is establishing a common GCD clock domain that all arbitrary clock domains synchronize to before serialization, which maintains PLL lock stability while achieving high-resolution deterministic phase alignment in modern PLL-based systems.
3Device complexity
If arbitrary clock domains are synchronized without GCD pre-synchronization, then system complexity is reduced, but high-resolution time domain alignment across multiple devices cannot be achieved
Solution Approach 1:
The patent introduces an intermediary GCD clock domain as a mediator between arbitrary clock domains and the serialization process. The GCD clock domain serves as a common reference that all other clock domains synchronize to, enabling high-resolution time domain alignment. This intermediary approach systematically manages the complexity by providing a structured synchronization hierarchy rather than direct peer-to-peer synchronization.
Data Source
AI summary
Methods and apparatus for multiple endpoint fine synchronization of arbitrary clock domains. An example apparatus (test module) includes a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC) having a target frequency of operation for input-out (IO) signals and programmable clock generation circuitry to generate a plurality of programmable clock signals including a reference clock (RefClk) signal that is correct for the target frequency of operation of IO signals. The module includes a plurality of synchronous devices such as pin electronic (PE) blocks that are configured to receive respective clock signals output from the programmable clock generation circuitry and generate and receive a respective set of IO signals associated with a respective clock domain. The respective sets of IO signals generated and received by the plurality of PE blocks are synchronized across the respective clock domains. One or modules may be implemented on instrument boards in a test system under which the IO signals across all clock domains are synchronized.