Heterogeneous FPGA Graph Processing Load Balancing
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Solution Overview
Problem
Existing FPGA-based graph processing systems are inefficient due to resource-intensive customization and long critical path times, which limits their ability to leverage high parallelism, and switching between CPU and FPGA processing is time-consuming and complex.
Innovation Solution
An optimization method for graph processing using a CPU+FPGA heterogeneous structure that dynamically assigns tasks based on power-law distribution properties, allowing the FPGA to process irregular data streams in parallel with the CPU, balancing processing loads and improving efficiency by using a shared storage module and scheduling module to integrate results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA-based graph processing uses customization, then adaptability is improved, but device complexity increases and critical path time becomes excessively long
Solution Approach 1:
The patent segments the graph processing system into CPU and FPGA components with distinct responsibilities. The CPU handles control flow and irregular data streams, while the FPGA handles parallel processing of regular data patterns. This segmentation allows customization benefits to be realized without requiring the entire system to be customized, thereby reducing overall device complexity and critical path time.
Solution Approach 2:
The patent implements dynamic task assignment where the system can adaptively decide whether to process data on CPU or FPGA based on real-time conditions. This dynamic approach allows the system to maintain adaptability for different graph processing scenarios while avoiding the fixed complexity of fully customized FPGA solutions, as the processing path can be adjusted without hardware reconfiguration.
2Productivity
If FPGA-based graph processing uses high parallelism, then productivity is improved, but resource consumption increases
Solution Approach 1:
The patent applies local quality by enabling high parallelism only in the FPGA component where it is most beneficial for regular data patterns, while the CPU handles irregular patterns with lower parallelism requirements. This localized application of high parallelism improves overall productivity without requiring the entire system to consume excessive resources, as each component uses parallelism appropriate to its processing needs.
3Adaptability or versatility
If CPU-FPGA heterogeneous structure switches between processors, then adaptability is improved, but loss of time increases due to switching overhead
Solution Approach 1:
The patent implements preliminary action by pre-processing graph data on the CPU to identify and separate regular and irregular data patterns before FPGA processing begins. This preliminary classification allows the system to maintain adaptability in handling different data types while minimizing switching time, as the data is already organized for optimal processing by each component without requiring frequent dynamic switching during execution.
Data Source
AI summary
The present invention relates to an optimization method for graph processing based on heterogeneous FPGA data streams. The method can balance processing loads between the CPU processing module and the FPGA processing module during acceleration of graph data processing.