FPGA GTP-U Packet Processing for Mobile Network Latency
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Solution Overview
Problem
Existing methods for processing General Packet Radio Service (GPRS) tunneling protocol user plane (GTP-U) packets in mobile networks face limitations in achieving low packet delay and high-performance traffic processing due to software implementation dependencies on CPU processing performance.
Innovation Solution
A method and apparatus for high-speed processing of GTP-U packets using a hardware-based packet processing apparatus, specifically a Field Programmable Gate Array (FPGA) unit, which generates a learning table for encapsulation or decapsulation independently of the mobile core network, utilizing IP information, tunneling endpoint identifiers, and GTP-C packets to optimize packet processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If software implementation method is used for LBO in MEC, then ease of operation is improved, but productivity is worsened due to CPU processing performance limitations
Solution Approach 1:
The patent replaces the software-based CPU processing system with a hardware-based Field Programmable Gate Array (FPGA) system. This substitution transforms the packet processing mechanism from software execution dependent on CPU performance to hardware logic execution that operates independently and at higher speeds, thereby resolving the contradiction between ease of operation and productivity
Solution Approach 2:
The patent changes the fundamental processing parameter from software execution time to hardware logic propagation time. By implementing packet processing logic in FPGA hardware, the processing speed parameter is dramatically improved while maintaining operational simplicity through configurable hardware logic that can be programmed to handle different packet processing scenarios
2Productivity
If hardware-based processing is used for GTP-U packets, then productivity is improved, but device complexity is worsened
Solution Approach 1:
The patent segments the packet processing function into distinct hardware modules within the FPGA, including separate logic for GTP-U packet decapsulation, learning table generation, and GTP-U packet encapsulation. This modular segmentation allows each component to be optimized independently while working together to achieve high-speed processing, thereby managing device complexity through structured design
Solution Approach 2:
The patent introduces a learning table as an intermediary data structure that stores mapping information between inner IP addresses and outer IP addresses. This intermediary component simplifies the encapsulation and decapsulation logic by providing pre-computed routing information, reducing the complexity of real-time packet processing while maintaining high productivity
Data Source
AI summary
Disclosed are a method and apparatus for high-speed processing of GTP-U packets in a mobile network. The packet processing method and the apparatus according to an embodiment implements the encapsulation or decapsulation of GTP-U packets in a mobile network in a hardware-based structure to process the LBO of the GTP-U packet at high speed. It achieves the processing and solves the difficulty of protocol interworking with the mobile core network as information for the encapsulation or decapsulation processing of the GTP-U packet independently is acquired through self-learning without the help of the mobile core network.