FPGA Walsh-Hadamard RACH Detection With Fewer Clock Cycles
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Solution Overview
Problem
Current systems for detecting rows or columns of Hadamard matrices in telecommunications require a large number of operation steps and clock cycles, which can delay the response to mobile units in 3G mobile telephone systems, particularly during the random access channel preamble detection process.
Innovation Solution
A configuration using a Walsh Hadamard Transform (WHT) with minimal add/subtract circuit blocks is implemented, employing shift registers and selectable add/subtract circuits to reduce the number of operations required, with parallel shift registers and multiplexers to minimize clock cycles, ideally suited for Field Programmable Gate Arrays (FPGAs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional correlation methods are used to detect Hadamard matrix rows, then detection accuracy is maintained, but the number of operation steps and clock cycles increases significantly
Solution Approach 1:
The detection process is segmented into multiple stages, where each stage processes a portion of the Hadamard matrix rows. The WHT circuit divides the computation into log2(N) stages, with each stage handling a subset of correlations, thereby reducing the total number of sequential operation steps while maintaining complete detection coverage.
Solution Approach 2:
The patent transforms the traditional one-dimensional sequential correlation approach into a multi-dimensional parallel processing structure using the WHT algorithm. By organizing computations in a butterfly pattern across multiple stages and utilizing parallel add/subtract circuits, the system processes multiple correlations simultaneously, reducing clock cycles from O(N) to O(log2(N)) stages.
2Productivity
If more logic circuits are added to perform correlation operations, then detection capability is improved, but the number of clock cycles and response time increases
Solution Approach 1:
Multiple correlation operations are merged into a unified WHT circuit structure. Instead of implementing separate correlators for each Hadamard row, the patent combines all correlation computations into a single WHT engine that processes all rows simultaneously through shared add/subtract circuits and multiplexers, reducing overall logic requirements while improving response time.
Solution Approach 2:
The system performs preliminary organization of the Hadamard matrix structure into a form suitable for WHT processing. The matrix is pre-arranged in a specific pattern that enables the butterfly computation structure to operate efficiently, allowing the detection circuit to proceed directly through the optimized WHT stages without requiring additional preprocessing logic.
3Device complexity
If sequential processing is used to minimize logic circuits, then device complexity is reduced, but the number of clock cycles increases
Solution Approach 1:
The WHT circuit maintains continuous useful action across all clock cycles by ensuring that every stage is actively performing computations. Parallel add/subtract circuits operate simultaneously in each stage, and multiplexers continuously switch between different data paths, eliminating idle cycles and maximizing the utilization of logic resources throughout the detection process.
Solution Approach 2:
The detection process employs periodic action through the staged WHT computation, where each stage operates in a repeating pattern of add and subtract operations. The butterfly structure creates a periodic computation rhythm that alternates between different mathematical operations across stages, enabling efficient time-multiplexed processing that reduces total clock cycles compared to purely sequential approaches.
Data Source
AI summary
A configuration for FPGA logic is provided to perform random access channel (RACH) preamble detection used in 3G mobile communications to identify individual rows of a Hadamard matrix using a Walsh Hadamard Transform (WHT). The configuration provides minimal add/subtract circuit blocks for the WHT by using stages, each stage containing a shift register connected to an add/subtract circuit. The shift register has outputs provided from a tap into its nth and n/2 elements, the outputs being connected to an add/subtract circuit, wherein n is the order of the Hadamard matrix. In a further embodiment parallel connected shift registers are used in each stage to increase operation speed.