FPGA Configuration Handshake Circuit Without Firmware Changes
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Solution Overview
Problem
Changing an FPGA in an electronic circuit requires significant firmware modifications, which is time-consuming and inefficient.
Innovation Solution
An electronic circuit design that includes a processor, a first FPGA, a reset signal generation circuit, and a dummy signal generation circuit, allowing the first FPGA to configure and complete its operation before the processor activates, using dummy signals to mimic the original completion and reset signals, thus avoiding the need for firmware changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the FPGA is changed to a different model, then the functionality and performance of the electronic circuit can be improved, but the firmware must be modified which increases development time and complexity
Solution Approach 1:
The patent applies preliminary action by configuring the FPGA before the processor is activated. The FPGA configuration is performed in advance during system initialization, allowing the processor firmware to remain unchanged while the FPGA can be swapped to different models. This preliminary configuration approach eliminates the need for firmware modifications when changing FPGA models.
Solution Approach 2:
The patent introduces an intermediary mechanism through a specific signal interface between the FPGA and processor. The FPGA outputs a completion signal to a dedicated input terminal on the processor, serving as an intermediary that communicates configuration status without requiring firmware changes. This intermediary signal interface allows different FPGA models to work with the same processor firmware.
2Speed
If the FPGA configuration is performed after processor activation, then the processor can start executing firmware immediately, but the FPGA may not be ready causing operational failures
Solution Approach 1:
The patent implements preliminary action by completing the FPGA configuration before the processor is activated. The system waits for the FPGA configuration completion signal before allowing the processor to start executing firmware, ensuring the FPGA is fully ready and configured, thus maintaining both fast processor activation and high reliability.
Solution Approach 2:
The patent uses feedback mechanism where the FPGA outputs a completion signal to the processor's input terminal. This feedback signal informs the processor when the FPGA configuration is complete, allowing the processor to wait appropriately before activation. This feedback loop ensures reliable coordination between FPGA configuration and processor activation timing.
3Reliability
If the processor waits for FPGA configuration completion, then the FPGA can be properly initialized, but the processor activation is delayed
Solution Approach 1:
The patent resolves this contradiction by performing the FPGA configuration as a preliminary action during system initialization before processor activation. The processor is designed to wait for the FPGA configuration completion signal, but this waiting period is part of the initialization sequence rather than a delay during operation. The FPGA configuration is completed in advance, ensuring reliable initialization without operational delays.
Data Source
AI summary
Provided is an electronic circuit that makes a changed FPGA usable without changing firmware. The electronic circuit includes: a processor; a first field-programmable gate array (FPGA); a first generation circuit; and a second generation circuit. The first FPGA executes configuration according to first bitstream data before the processor is activated. The first generation circuit outputs a first reset signal that resets the processor to the processor based on a first completion signal indicating that the configuration is completed. The second generation circuit outputs a second completion signal indicating that the configuration is completed to the processor based on a control signal output from the processor.