FPGA Hardware Accelerator for Automated Test Equipment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional automated test equipment (ATE) systems are limited by the processing capabilities of the tester processor and fixed communication protocols, restricting the number and type of devices under test (DUTs) that can be simultaneously tested, and require time-consuming re-programming of FPGAs for protocol changes.
Innovation Solution
A test architecture that transfers command and test pattern generation functionality to FPGAs, using host bus adapters (HBAs) with protocol converter modules to provide protocol flexibility, allowing FPGAs to support multiple protocols and enabling rapid switching between protocols without re-programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If command and test pattern generation functionality is transferred to FPGAs, then processing load on tester processor is reduced and test throughput is improved, but device complexity increases due to FPGA configuration and host bus adapter integration
Solution Approach 1:
The system divides functionality between the tester processor and FPGAs by segmenting command generation and data handling tasks. The tester processor handles high-level test control while FPGAs perform parallel command and pattern generation, enabling distributed processing that improves throughput without requiring complete system redesign
Solution Approach 2:
Host bus adapters serve as intermediaries between the tester processor and FPGAs, managing communication protocols and data transfer. This intermediary layer simplifies the overall architecture by providing standardized interfaces and protocol conversion, reducing the complexity burden of direct FPGA integration
2Adaptability or versatility
If FPGAs are re-programmed for protocol changes, then protocol flexibility is achieved, but time consumption increases due to re-programming requirements
Solution Approach 1:
The system implements dynamic protocol adaptation through host bus adapters that can switch between different communication protocols (PCIe, USB 3.0, SATA, SAS) without requiring FPGA re-programming. This dynamic configuration allows the same physical hardware to adapt to different protocol requirements through software/firmware updates rather than hardware reconfiguration
Solution Approach 2:
Host bus adapters act as protocol translation intermediaries, converting between different communication protocols at the bus level rather than requiring protocol-specific FPGAs. This intermediary approach enables protocol flexibility through the adapter layer while keeping the FPGA interface stable and unchanged
3Reliability
If fixed hardware bus adapter sockets are used, then hardware compatibility is ensured, but adaptability to different communication protocols is limited
Solution Approach 1:
The system implements universal adaptability by making the host bus adapter configurable to support multiple communication protocols (PCIe, USB 3.0, SATA, SAS) through a single physical interface. This multi-functional adapter can be dynamically configured to match different DUT requirements without changing the physical hardware connection, maintaining reliability while expanding protocol support
Solution Approach 2:
The host bus adapter's protocol configuration is changed through software or firmware parameter updates rather than hardware modifications. By changing the operational parameters of the adapter, the system can switch between different protocols while maintaining the same physical hardware compatibility and connection interface
Data Source
AI summary
An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.