FPGA Hardware Accelerators for ATE SSD Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional automated test equipment (ATE) systems are limited in their ability to efficiently test devices under test (DUTs) with odd sector sizes and protection modes, as they require reconfiguration of hardware and do not support non-standard sector sizes or protection features, leading to increased testing time and reduced throughput.
Innovation Solution
The solution involves transferring command and test pattern generation functionality to Field-Programmable Gate Arrays (FPGAs), allowing for reconfigurable communication protocols and support for various sector sizes and protection modes, thereby reducing processing load on the tester processor and enabling simultaneous testing of multiple DUTs with different protocols and configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional ATE systems use fixed hardware bus adapter cards for specific communication protocols, then the system can test devices with standard protocols, but the system cannot test devices with different protocols without hardware reconfiguration
Solution Approach 1:
The patent implements dynamic protocol adaptation by replacing fixed hardware bus adapter cards with software-configurable protocol handlers that can be programmed to support different communication protocols on demand, allowing the ATE system to dynamically adapt to various device protocols without physical hardware changes
Solution Approach 2:
The patent changes the parameter of protocol support from fixed hardware configuration to software-configurable parameters, enabling the system to switch between different communication protocols by modifying software parameters rather than physical hardware
2Productivity
If the tester processor generates all commands and test patterns, then the system can maintain simple architecture, but the processing load and bandwidth requirements limit the number of DUTs that can be tested simultaneously
Solution Approach 1:
The patent segments the command and test pattern generation functionality from the tester processor and relocates it to the FPGA device, dividing the processing workload between the tester processor (which generates test programs) and the FPGA (which generates actual commands and patterns locally), thereby reducing the processing load and bandwidth requirements on the tester processor
Solution Approach 2:
The patent moves the command generation function from the central tester processor to the distributed FPGA device, adding a spatial dimension to the architecture where each FPGA operates semi-independently to generate its own test patterns, reducing contention for processor resources
3Adaptability or versatility
If conventional ATE systems test devices with standard sector sizes, then the testing process is straightforward, but the systems cannot test devices with odd sector sizes or protection modes
Solution Approach 1:
The patent implements support for odd sector sizes and protection modes by configuring the FPGA device with custom parameters for sector size and protection mode, allowing the test system to adapt to various device specifications while maintaining accurate testing through proper parameter setup
Data Source
AI summary
An automated test equipment (ATE) apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The tester processor is operable to generate commands and data from instructions received from the system controller for coordinating testing of a device under test (DUT), wherein the DUT supports a plurality of non-standard sector sizes and a plurality of protection modes. The FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT, and wherein the at least one hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes.