FPGA IC Emulation Clock Model Glitch Elimination
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Solution Overview
Problem
The challenge in emulating Integrated Circuit (IC) designs on Field-Programmable Gate Arrays (FPGAs) arises from the difference in clock structures between ICs and FPGAs, leading to glitches in generated clocks that cause errors in sequential cells, which cannot be controlled through wiring design in FPGAs as they can in ICs.
Innovation Solution
The method involves identifying and grouping sequential cells into groups A and B, modifying them with specific clock models [CA] and [CB] that connect glitch-containing user clocks to glitch-insensitive user enables, and configuring a primary clock′ to eliminate glitches, thereby reducing clock domains and resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IC design is directly applied on FPGA, then the design can be implemented on FPGA platform, but glitches cannot be controlled because FPGA is a pre-wired semi-custom circuit that does not allow wiring length adjustment
Solution Approach 1:
The patent changes the parameter of clock signal processing by introducing delay elements and synchronization stages. Instead of controlling glitches through wiring length (IC approach), the patent uses configurable delay parameters and synchronization parameters in the clock management circuit to control the timing and eliminate glitches when transitioning from IC to FPGA platform.
Solution Approach 2:
The patent introduces a clock management circuit as an intermediary between the IC design and FPGA implementation. This intermediary circuit includes delay elements, synchronization stages, and clock distribution logic that mediate the clock signal transitions, allowing the design to adapt to FPGA's pre-wired structure while maintaining glitch control through software-configurable parameters.
2Device complexity
If generated clocks with glitches are connected to sequential cell clock input, then the clock structure can be implemented, but the sequential cell is mistakenly triggered to sample signals resulting in error of data sample output
Solution Approach 1:
The patent applies preliminary action by introducing synchronization stages and delay elements before the clock signal reaches the sequential cell. These preliminary processing stages clean up the clock signal by eliminating glitches and synchronizing the clock edges, ensuring that sequential cells are only triggered by clean, synchronized clock signals, thus preventing erroneous data sampling.
Solution Approach 2:
The patent converts the harmful effect of glitches into a benefit by using the glitch detection capability to trigger synchronization mechanisms. The presence of glitches in generated clocks is detected and used as a signal to activate delay elements and synchronization stages that eliminate the glitches, thereby improving overall system reliability.
Data Source
AI summary
The invention relates to the technical field of electronic design automation (EDA), specially relates to a method and a system for emulating IC design with an FPGA, and a storage medium. By identifying ports of sequential cells, the sequential cells are labeled as group A and group B according to the conditions that a data output of a sequential cell is connected to a user clock input of another sequential cell or is not connected to the user clock input of the other sequential cell but is connected to a data input of the other one sequential cell. All sequential cells in the group A is substituted with clock models[CA], and all sequential cells in the group B is substituted with clock models[CB]. The clock model[CA] and the clock model[CB] solve glitch problem by connecting glitch-containing user clock to a user enable non-sensitive to glitch. By configuring primary clocks′, each of the group A and the group B is driven by a primary clock′, thereby reducing numbers of clock domains, and the whole system can be simultaneously started-up and paused by controlling the primary clocks′.