FPGA CNN Image Buffer Layout for Continuous DDR Access
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Solution Overview
Problem
The existing method of implementing FPGA CNN convolution data extraction by buffering image data to off-chip DDR memory results in low reading and writing rates due to multiple address jumps and non-continuous data access, which limits the image processing rate.
Innovation Solution
An image data storage method that sequentially stores image data in a dynamic random memory with continuous storage addresses, followed by reading and processing the data in a first-input first-output memory of an FPGA to reduce read-write delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If image data is buffered to off-chip DDR memory and read in small pieces with multiple address jumps, then the FPGA can perform convolution operations, but the reading and writing rate of DDR memory is low
Solution Approach 1:
The patent applies preliminary action by pre-processing the image data storage format before convolution operations. Specifically, it organizes image data into a continuous memory layout where pixel values are arranged sequentially in memory (e.g., all pixel values of one channel followed by the next channel), eliminating the need for random address jumps during convolution. This preliminary organization of data in continuous memory enables high-speed sequential reading during processing, directly resolving the contradiction between memory access speed and image processing throughput
2Productivity
If multiple small pieces of non-continuous data are read from DDR memory, then convolution operations can be performed, but the read-write capability of DDR cannot be fully unleashed
Solution Approach 1:
The patent implements continuity of useful action by ensuring continuous data access patterns in DDR memory. The image data is stored in a continuous format where adjacent pixel values occupy adjacent memory locations, allowing the memory controller to read data sequentially without interruption for address changes. This continuous access pattern fully utilizes the DDR memory's read-write capability and eliminates time losses associated with address jumping, directly addressing the contradiction between productivity and time loss
Data Source
AI summary
Provided are an image data storage method, an image data processing method and system, and a related apparatus. The image data processing method includes the following steps: sequentially storing image data in a dynamic random memory according to a preset storage format, so that adjacent pieces of image data in the dynamic random memory have continuous storage addresses; reading a preset number of pieces of multi-channel parallel image data from the dynamic random memory, and storing the multi-channel parallel image data in a first-in first-out memory of an FPGA; and executing a convolution operation on target image data in the first-in first-out memory to obtain image feature data. By means of the method, the image data processing rate can be increased.