Inferred Logic Connections for FPGA Partial Reconfiguration
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Solution Overview
Problem
Dynamic partial reconfiguration in FPGAs is complex due to the need for bus macros, which are difficult to use, introduce additional delay, and consume resources, making it challenging to ensure proper connectivity between dynamically reconfigurable regions and other parts of the circuit.
Innovation Solution
A method is introduced to infer logic connections between dynamically reconfigurable modules (DRMs) and external logic based on attributes, allowing for automatic generation of circuit elements like lookup tables and flip-flops, reducing the need for bus macros and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bus macros are used to ensure proper connectivity between dynamically reconfigurable regions and other parts of the circuit, then connectivity is ensured, but device complexity and resource consumption increase
Solution Approach 1:
The patent extracts the connectivity assurance function from complex bus macros and implements it through simple inferred logic connections. The system automatically infers necessary logic connections between dynamically reconfigurable modules and external logic based on module attributes, eliminating the need for manual bus macro insertion while maintaining proper connectivity.
Solution Approach 2:
The design flow performs self-service by automatically inferring logic connections without requiring manual intervention. The system analyzes module attributes and automatically generates the necessary logic connections, eliminating the need for designers to manually create bus macros and perform complex wiring operations.
2Reliability
If bus macros are used to ensure proper connectivity, then connectivity is ensured, but additional delay is introduced
Solution Approach 1:
The patent replaces expensive, complex bus macros with simple, lightweight inferred logic connections. These inferred connections act as disposable, minimal-logic elements that provide the necessary connectivity without the overhead of full bus macro implementations, thereby reducing propagation delay.
3Reliability
If bus macros are used to ensure proper connectivity, then connectivity is ensured, but resource consumption increases
Solution Approach 1:
The patent extracts only the essential connectivity function from bus macros and implements it through minimal inferred logic. This extraction eliminates the need for full bus macro resources while maintaining the critical connectivity function between dynamically reconfigurable modules and external logic.
Solution Approach 2:
Instead of using heavy bus macro structures, the system creates lightweight copies of connectivity logic through inference. The inferred logic connections replicate the essential wiring function without the resource overhead of actual bus macro implementations.
4Reliability
If manual wiring of bus macros is performed, then connectivity is ensured, but ease of operation decreases
Solution Approach 1:
The system performs self-service by automatically inferring logic connections based on module attributes. This eliminates the need for designers to manually wire bus macros, significantly improving ease of operation while ensuring proper connectivity through automated analysis and generation of connection logic.
Solution Approach 2:
The system performs preliminary action by pre-analyzing module attributes and pre-generating the necessary logic connections before the design implementation phase. This preliminary inference work eliminates the need for manual wiring operations during the design process.
Data Source
AI summary
A method of processing a logical netlist for implementing a circuit design within a programmable integrated circuit includes identifying a dynamically reconfigurable module (DRM) comprising a port from the logical netlist. The DRM defines a dynamically reconfigurable region of the integrated circuit that communicates with a module that is not dynamically reconfigurable via the port. First circuitry of the DRM and circuitry external to the DRM are implemented. The first circuitry connects to the circuitry external to the DRM via the port. The circuitry external to the DRM is within the module that is not dynamically reconfigurable. The method further includes locking routing resources connecting the circuitry external to the DRM to a location associated with a boundary of the DRM for the port; and implementing second circuitry of the DRM by reusing the locked routing resources. The second circuitry is routed to connect to the location associated with the boundary of the DRM for the port.