FPGA iNOC Routing for 400G Ethernet Congestion Relief
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Solution Overview
Problem
Traditional Field Programmable Gate Arrays (FPGAs) face challenges in handling high-throughput Ethernet networking due to lower operating frequencies of user logic, leading to congestion and difficulty in meeting timing requirements, especially with high-speed interfaces like 400 Gbps Ethernet.
Innovation Solution
The implementation of an internal network on chip (iNOC) within the FPGA core, which efficiently load-balances Ethernet traffic, allows data movement without requiring data movement registers in FPGA logic, and rearranges packet data to utilize typical clock speeds, supporting multiple Ethernet modes and reducing transport frequency through features like quad segment interface and cut-through mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If networking IP cores are located at the boundary of the FPGA core, then high-speed Ethernet interfaces (400 Gbps) can be supported, but significant congestion issues occur and timing requirements become difficult to meet
Solution Approach 1:
The patent introduces a three-dimensional mesh network architecture that adds spatial dimensions (rows and columns) to data routing. Instead of linear boundary-to-core paths, data can traverse multiple dimensional paths through the FPGA fabric, distributing traffic across row and column interconnects to eliminate congestion bottlenecks while maintaining 400 Gbps interface speeds.
Solution Approach 2:
The patent introduces network routers as intermediary nodes within the FPGA fabric that mediate data flow between boundary interfaces and core logic. These routers buffer, forward, and manage packet routing through the mesh network, preventing direct congestion at the boundary while enabling efficient core access through distributed routing paths.
2Adaptability or versatility
If logic is crowded around the networking interface to support high-throughput applications, then networking functionality is enhanced, but congestion issues worsen and timing requirements become harder to meet
Solution Approach 1:
The patent segments the networking functionality by distributing IP cores and logic across multiple clusters throughout the FPGA fabric rather than concentrating them at the boundary. Each cluster can independently handle networking tasks, distributing complexity across the device while maintaining high adaptability for various networking applications through the mesh network connectivity.
Data Source
AI summary
Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.