FPGA Tile-to-Tile Interconnect Routing for Congestion Conflicts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FPGA routing techniques face challenges in efficiently and rapidly establishing desired interconnect architectures between logic tiles, particularly in handling conflicts and congestion within the tile-to-tile interconnect network, which affects communication efficiency and signal timing.
Innovation Solution
The proposed technique involves routing partial interconnect paths independently for subsets of logic tiles, allowing for parallel and concurrent configuration of tile-to-tile interconnects, including re-routing steps to address conflicts and congestion, ensuring efficient communication paths between computing elements across the FPGA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential routing techniques are used to establish tile-to-tile interconnects, then routing completeness can be achieved, but routing speed and efficiency are reduced
Solution Approach 1:
The patent divides the routing process into independent segments by organizing logic tiles into multiple subsets and routing interconnects for each subset independently and in parallel. This segmentation enables simultaneous processing of multiple routing tasks, dramatically improving routing speed while maintaining completeness through systematic coverage of all tile subsets.
2Productivity
If parallel routing configuration is implemented for multiple logic tile subsets, then routing efficiency is improved, but handling conflicts and congestion becomes more complex
Solution Approach 1:
The patent performs preliminary actions by pre-organizing logic tiles into multiple subsets and establishing independent routing configurations for each subset before full system operation. This preliminary organization enables parallel processing while conflicts are detected and resolved through re-routing steps, managing complexity through structured preparation rather than ad-hoc conflict resolution.
Solution Approach 2:
The patent implements feedback mechanisms through re-routing steps that detect conflicts and congestion in parallel routing configurations and automatically adjust interconnect paths. When conflicts are identified in one subset, the system provides feedback to modify routing decisions, enabling dynamic resolution of complexity while maintaining parallel efficiency.
3Reliability
If independent routing of partial interconnect paths is performed for each logic tile subset, then communication efficiency between tiles is improved, but ensuring end-to-end connectivity across all subsets becomes more difficult
Solution Approach 1:
The patent merges independent routing results from multiple logic tile subsets into a unified end-to-end interconnect architecture. By combining the independently routed partial interconnect paths through a coordinated system that ensures compatibility and connectivity across subset boundaries, the patent achieves both local communication efficiency and global end-to-end connectivity without requiring complex centralized routing management.
Data Source
AI summary
A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively. Routing the second plurality of tile-to-tile interconnects includes connecting at least one start/end point of each tile-to-tile interconnect in the second plurality of tiles to at least one start/end point of each interconnect in the first plurality of tiles.