Time-Multiplexed FPGA Interconnect to Cut Routing Silicon Area
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Solution Overview
Problem
Programmable logic devices, such as FPGAs, face significant silicon overhead due to extensive routing wires, leading to increased costs and performance disparities compared to ASICs, with over 90% of configurability dedicated to interconnects and only 10% to logic configuration, resulting in large chip area penalties.
Innovation Solution
Implementing a programmable time multiplexing scheme that allows multiple inputs and outputs to share a single wire, reducing the overall number of wires required and integrating configurability into vertical configuration circuits, along with 3D integration of pass-gate and configuration circuits to minimize silicon real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If extensive routing wires are used to provide programmability in FPGAs, then reconfigurability and flexibility are improved, but silicon area and cost increase significantly
Solution Approach 1:
The patent segments the routing wires into multiple segments that can be time-multiplexed. Instead of providing dedicated wires for all possible connections, the routing is divided into segments that can be activated at different times, reducing the total wire count while maintaining reconfigurability
Solution Approach 2:
The patent introduces dynamic time-multiplexed control signals that allow a single physical wire to carry multiple logical connections at different times. The routing structure transitions from static dedicated wires to dynamic shared wires controlled by time-multiplexed select signals, reducing silicon area while preserving adaptability
2Device complexity
If dedicated wires are provided for each input and output signal, then routing simplicity is improved, but the number of wires and silicon overhead increase
Solution Approach 1:
The patent makes each routing wire universal by enabling it to serve multiple functions at different times through time-multiplexing. A single wire can connect different input-output pairs at different times, controlled by time-multiplexed select signals, reducing the total number of wires needed while maintaining routing flexibility
Solution Approach 2:
The patent employs periodic time-multiplexed control signals to systematically activate different routing paths at different time intervals. The periodic nature of the control signals ensures that each wire segment is activated in its designated time slot, enabling efficient sharing of wire resources without conflict
3Area of stationary object
If time multiplexing is implemented to share wires, then silicon area is reduced, but timing predictability and signal integrity must be maintained
Solution Approach 1:
The patent incorporates preliminary timing control by using synchronized time-multiplexed select signals that are generated in advance and distributed throughout the routing structure. This preliminary timing control ensures that wires are activated and deactivated at precise moments, maintaining timing predictability despite the shared nature of the routing resources
Data Source
AI summary
A time multiplexed programmable switch of a semiconductor device comprising: a first node; and a plurality of second nodes, each of the second nodes having a path to couple to the first node, the path comprising: a first configurable device configured to select or deselect the path; and a second configurable device in series with the first configurable device configured to select or deselect the path by a digital signal; wherein, the plurality of digital signals are time multiplexed to have no more than one second device in the select state within a time interval.