FPGA-Based Interface Apparatus for Semiconductor Test Yield

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Solution Overview

Problem

Conventional semiconductor testing methods are limited by the need for expensive, high-end testers for back-end testing after assembly and packaging, leading to increased complexity and cost, and inefficient front-end testing that results in yield overkill and wasted resources due to the inability to perform high-speed datasheet testing at the wafer level.

Innovation Solution

The use of advanced probe cards and load boards equipped with Field Programmable Gate Array (FPGA) daughter cards that enable high-speed testing of semiconductor wafers and packaged devices, allowing for both front-end and back-end testing with programmable logic circuits and memory, reducing the need for expensive testers and improving yield by identifying defective devices early.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional front-end testing using slow testers is used, then cost is reduced and simplicity is improved, but testing speed is limited and high-speed functional tests cannot be performed

Engineering Contradiction:

Improvetester complexityVSAvoidtesting speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The testing system is segmented into two independent parts: a slow front-end tester for basic functional tests and a fast back-end tester for high-speed functional tests. This allows each tester to be optimized for its specific speed range without requiring one tester to handle all speed requirements, thus reducing the complexity of the front-end tester while enabling high-speed testing capability in the overall system.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The back-end tester is designed with multi-functionality to perform both parametric tests and high-speed functional tests that the front-end tester cannot handle. This universal tester consolidates multiple testing capabilities into one system, allowing the front-end tester to remain simple while the back-end tester provides comprehensive high-speed testing functionality.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Speed

If back-end testing using expensive high-end testers is used, then high-speed functional tests and parametric tests can be performed, but cost increases and device complexity increases

Engineering Contradiction:

Improvetesting speedVSAvoidtester complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

3Ease of manufacture

If front-end testing with slow testers is used, then cost is reduced, but yield efficiency decreases due to inability to perform high-speed tests at wafer level

Engineering Contradiction:

Improvemanufacturing costVSAvoidyield efficiency

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The system performs preliminary functional tests at the front-end wafer level using the slow tester to identify obviously defective devices before they undergo expensive packaging. This preliminary screening action prevents defective devices from entering the packaging process, improving yield efficiency while keeping costs low by using the simpler front-end tester for initial screening.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The probe card assembly serves as an intermediary that physically connects the slow front-end tester to the devices on the wafer, enabling functional tests to be performed at the wafer level despite the tester's speed limitations. This intermediary allows the system to perform preliminary screening at low cost while maintaining the ability to identify defective devices before packaging.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Speed

If offset technique is used to compensate for speed difference, then high-speed tests can be attempted at front-end, but yield overkill occurs and good devices are culled

Engineering Contradiction:

Improvetesting speedVSAvoiddevice yield

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS7906982B1Interface apparatus and methods of testing integrated circuits using the same

Publication Date: 2011.03.15 INFINEON TECHNOLOGIES LLC

AI summary

An apparatus and method are provided for testing a semiconductor device (DUT). Generally, the apparatus includes an interface board with conductive elements adapted to electrically couple with the DUT and connected to a number of test circuits. Each test circuit resides on one of a number of daughter cards on the interface board, and provides test input signals to and receives output signals from the DUT to generate a result based on a program loaded to the daughter cards before testing begins. The apparatus further includes a controller to drive the interface board and store test results. In one embodiment, the interface board is a load board for back end testing. In another embodiment, the interface board is a probe card for front end testing. Preferably, the apparatus is capable of testing DUTs including memory arrays, logic circuits or both, and the daughter cards are capable of being re-programmed and re-used on different DUTs.