FPGA Internal Phase Control Without Clock Domain Crossing Delay
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face a technical challenge in synchronizing receiver and transmitter clock signals, leading to unwanted latency and processing delays, particularly in high-frequency applications like high-frequency trading where microsecond accuracy is crucial.
Innovation Solution
A field programmable gate array system with an internal phase controller that includes a phase detector and phase controller to align the receiver and transmitter clock signals, eliminating the need for clock domain crossing circuits and minimizing latency by adjusting the phase of the transmitter side clock to match the receiver side clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock domain crossing circuits are used to synchronize receiver and transmitter clock signals, then phase synchronization is achieved, but processing delay increases
Solution Approach 1:
The patent extracts the phase adjustment function from traditional clock domain crossing circuits and implements it through a dedicated phase detector and phase controller that operate independently. This allows phase synchronization to be achieved without the full overhead of conventional CDC circuitry, reducing processing delay while maintaining synchronization reliability.
Solution Approach 2:
The phase detector continuously monitors the phase relationship between receiver and transmitter clocks in advance, and the phase controller proactively adjusts the transmitter clock phase before significant misalignment occurs. This preliminary action prevents synchronization errors without requiring reactive delay-introducing correction mechanisms.
2Reliability
If traditional phase-locked loop circuits are used for clock synchronization, then frequency and phase matching is achieved, but device complexity increases
Solution Approach 1:
The patent segments the traditional PLL circuit into distinct functional modules: a phase detector that specifically measures phase differences, and a phase controller that independently adjusts the transmitter clock. This segmentation eliminates unnecessary frequency multiplication and division stages, reducing circuit complexity while maintaining synchronization reliability.
Solution Approach 2:
The phase detector and phase controller form a self-regulating system where the phase detector automatically detects phase errors and the phase controller autonomously corrects them by adjusting the transmitter clock phase. This self-service mechanism eliminates the need for complex external control logic and reduces overall device complexity.
Data Source
AI summary
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.