Internal PLL Clock Alignment in FPGAs for Sub-Microsecond Latency

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Solution Overview

Problem

Field programmable gate arrays (FPGAs) face a technical challenge in synchronizing receiver and transmitter clock signals, leading to unwanted latency and processing delays, particularly in high-frequency applications like high-frequency trading where microsecond accuracy is crucial.

Innovation Solution

A field programmable gate array system with an internal or external phase controller that aligns the receiver and transmitter clock signals by using a phase detector and controller to adjust the phase difference, eliminating the need for clock domain crossing circuits and minimizing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If clock domain crossing circuits are used to synchronize receiver and transmitter clocks, then phase synchronization is improved, but processing delay increases

Engineering Contradiction:

Improvephase synchronizationVSAvoidprocessing delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the phase synchronization function from traditional clock domain crossing circuits and implements it through a dedicated phase detector and phase adjustment mechanism. This separates the synchronization function from the data path, allowing phase alignment without introducing delay into the critical processing path.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a phase detector as an intermediary component that monitors the phase difference between receiver and transmitter clocks and generates adjustment signals. This intermediary mechanism enables precise phase control without requiring complex clock domain crossing circuits that would delay processing.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If phase alignment is implemented between receiver and transmitter clocks, then data integrity is improved, but system complexity increases

Engineering Contradiction:

Improvedata integrityVSAvoidsystem complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the clock synchronization system into distinct functional blocks: a phase detector that measures phase difference, a phase adjustment mechanism that modifies the transmitter clock phase, and control logic that coordinates their operation. This modular segmentation makes the system more manageable and implementable while maintaining data integrity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a feedback loop where the phase detector continuously monitors the phase relationship between receiver and transmitter clocks and feeds adjustment signals back to the phase adjustment mechanism. This closed-loop feedback system automatically maintains phase alignment without requiring complex external control, improving data integrity while keeping system complexity manageable.

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables sub-microsecond processing throughput without introducing unnecessary delays, ensuring efficient data processing and transmission across the FPGA system.

Implementation Method 1

a phase detector configured to compare the phase of the receiver side clock signal and the phase of the transmitter side clock signal and to generate a phase difference indicator signal based on a difference between the phase of the receiver side clock signal and the phase of the transmitter side clock signal

Methodology Applied

Scientific EffectPhase detection:

Implementation Method 2

a phase controller configured to adjust the phase of the transmitter clock signal based on the phase difference indicator signal so that the phase of the receiver side clock signal and the phase of the transmitter side clock signal are aligned

Methodology Applied

Scientific EffectPhase adjustment: