Automated Interrupt Request Provisioning in FPGA Designs

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Solution Overview

Problem

Existing programmable logic device and ASIC designs lack automated provisioning for appropriate interrupt requests, requiring manual intervention by system designers.

Innovation Solution

A method to manage interrupt requests by capturing FPGA environmental constraints, generating connections among interrupt sources, controllers, and request ports, and automatically instantiating controller logic during compilation, especially when interrupt controllers are lacking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If manual provisioning of interrupt requests is used in FPGA designs, then design flexibility and control are maintained, but design time and complexity increase significantly

Engineering Contradiction:
ImproveEase of interrupt request provisioningVSAvoidDesign time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The compilation tool automatically detects IP cores requiring interrupt requests and generates the necessary controller logic and connections without designer intervention. The system serves itself by autonomously provisioning interrupt requests based on IP core metadata, eliminating manual configuration steps while maintaining design control.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs preliminary analysis during compilation to identify which IP cores need interrupt requests before the design is finalized. By detecting IP cores and their interrupt requirements in advance, the tool prepares the necessary controller logic and connections proactively, reducing design time and preventing omissions.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If manual provisioning of interrupt requests is used, then accuracy and control are maintained, but probability of design errors increases due to human oversight

Engineering Contradiction:
ImproveDesign accuracyVSAvoidDesign process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The compilation tool continuously monitors the design during compilation, detecting IP cores and analyzing their interrupt requirements. This feedback mechanism ensures that all necessary interrupt requests are identified and provisioned automatically, reducing human error while maintaining design accuracy through systematic verification.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The compilation tool acts as an intermediary between IP core developers and system integrators. It automatically translates IP core metadata into appropriate interrupt request configurations, eliminating the need for manual interpretation and reducing errors caused by human oversight while simplifying the design process.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If automated tools are implemented for interrupt request provisioning, then productivity and automation are improved, but tool complexity and development effort increase

Engineering Contradiction:
ImproveDesign productivityVSAvoidTool complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system uses IP core metadata and documentation as templates to automatically generate interrupt request configurations. By copying and adapting predefined patterns from IP core specifications, the tool automates the provisioning process without requiring complex custom logic, thereby improving productivity while keeping tool complexity manageable.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8079009B1Managing interrupt requests from IP cores
Publication Date: 2011.12.13 XILINX INC
  • US8079009B1 patent drawing
  • US8079009B1 patent drawing
  • US8079009B1 patent drawing

AI summary

A system and method of managing interrupt requests from IP cores within an integrated circuit design can include capturing environmental constraints within constraint files for the integrated circuit design (where the constraints can include information regarding a board upon which an integrated circuit device is mounted, pin locations for interrupt signals, and the sensitivity of the interrupt signals), generating connections among interrupt sources, interrupt controllers, and interrupt request ports on microprocessor cores within a device environment, and automatically instantiating controller logic when interrupt controllers are lacking during compilation of the device design. The method and system can also identify within the design, processor and bus interconnections as well as each interrupt port on the IP cores and the sensitivity requirements for each port which can be stored within description files for a corresponding IP core instead of an HDL specification.