FPGA Interval Division Using Counter Error Accumulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current interval equal division methods in measurement and control systems face challenges in achieving high precision and simplicity, often relying on complex crystal oscillator corrections and struggling to ensure precise synchronization with GPS or Beidou time information.
Innovation Solution
An FPGA-based design method that divides the oscillation periods of a second pulse signal by a number of equally divided sampling pulses, using a counter to accumulate and correct errors within each sampling interval, with correction formulas applied to maintain precision and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If crystal oscillator precision and correction methods are used for interval equal division, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the second pulse interval into N equal parts by segmenting the counting process. The counter accumulates clock cycles and generates sampling pulses at predetermined intervals, dividing the large second interval into manageable equal segments without complex correction mechanisms.
Solution Approach 2:
The system uses self-service by utilizing the crystal oscillator's own output signals (second pulse and clock signal) for both counting and timing operations. The counter automatically accumulates clock cycles and generates sampling pulses without requiring external correction inputs or additional precision components.
2Ease of operation
If simple interval equal division is implemented, then ease of operation is improved, but measurement precision deteriorates
Solution Approach 1:
The patent implements feedback by continuously monitoring the counter value and comparing it against predetermined thresholds. When the accumulated clock cycles reach a threshold value, the system generates a sampling pulse and resets the counter, creating a self-regulating feedback loop that ensures precise equal division while maintaining simple operation.
Solution Approach 2:
The system performs preliminary action by pre-calculating and storing threshold values for the counter based on the desired number of divisions N. These predetermined thresholds enable the simple counter to automatically generate precisely timed sampling pulses without requiring real-time complex calculations during operation.
3Reliability
If real-time updating with second pulse is implemented, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent ensures continuity of useful action by maintaining a continuous counting process that never stops. The counter continuously accumulates clock cycles from the crystal oscillator, and the second pulse continuously triggers new counting cycles, ensuring uninterrupted real-time updating and synchronization without time losses from restarts or reinitialization.
Data Source
AI summary
Provided is a FPGA-based design method for equally dividing an interval, including the following steps: dividing the oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by the number of equally divided sampling pulses, and obtaining the remainder thereof; dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; using a counter to count from the second pulse, and stopping the counting of the counter once whenever the error within the sampling interval, which is accumulated within the second pulse interval, is greater than or equal to the vibration period. Further provided is a FPGA-based design device for equally dividing an interval. The present application makes full use of the feature of interval equal division calculation, has high precision, and is easy to implement.