FPGA I/O Filtering Layer for Triggered Failure Capture

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Solution Overview

Problem

Conventional FPGA testing and debugging methods, such as JTAG, are limited in their ability to effectively monitor and modify input/output operations, especially in handling dynamic signal patterns and internal registers, and lack the flexibility to capture a wide range of signals simultaneously, which restricts comprehensive failure analysis.

Innovation Solution

The implementation of a logic layer between the FPGA I/O and core logic allows for the addition of a digital oscilloscope that can select trigger signals, acquire and store I/O signals, and generate timestamps, enabling the capture of catastrophic events and improving failure analysis by acting as a 'black box' for the FPGA.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional FPGA testing methods (JTAG) are used, then the testing process is simple, but the ability to monitor and modify I/O operations is limited

Engineering Contradiction:
Improvetesting process simplicityVSAvoidI/O monitoring and modification capability
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

A logic filtering layer is introduced as an intermediary component between the I/O pins and the core logic of the FPGA. This filtering layer includes programmable logic that can monitor, filter, and modify I/O signals without disrupting the core functionality. The intermediary layer enables comprehensive I/O observation and control while maintaining the simplicity of the original testing approach.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If a logic filtering layer is added between FPGA I/O and core logic, then I/O monitoring and modification capability is improved, but device complexity increases

Engineering Contradiction:
ImproveI/O monitoring and modification capabilityVSAvoidFPGA logic layer complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The FPGA logic is segmented into distinct functional layers: the core logic layer that performs the primary computational functions, and the filtering layer that handles I/O monitoring and modification. This segmentation allows each layer to be independently configured and optimized, reducing the complexity burden on the core logic while enabling sophisticated I/O control through the dedicated filtering layer.

Inventive Principle:
Principle #1Segmentation

3Reliability

If multiple I/O signals are captured simultaneously, then failure analysis capability is improved, but memory requirements and data processing complexity increase

Engineering Contradiction:
Improvefailure analysis capabilityVSAvoidmemory requirements
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The filtering layer performs preliminary processing of I/O signals by pre-configuring trigger conditions and filtering criteria before signals are captured. When predefined trigger conditions are met, the system captures only the relevant signal sequences and associated metadata. This preliminary action reduces the volume of data that needs to be stored and processed, while still providing comprehensive failure analysis capability.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If trigger-based signal acquisition is implemented, then the ability to capture catastrophic events is improved, but the complexity of signal acquisition control increases

Engineering Contradiction:
Improvecatastrophic event capture capabilityVSAvoidsignal acquisition control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The filtering layer incorporates self-service trigger mechanisms that automatically monitor I/O signals and initiate capture operations when predefined conditions are met. The system configures its own trigger conditions, acquisition parameters, and storage requirements without external intervention. This self-service capability enables reliable catastrophic event capture while minimizing the complexity of external control systems.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10248585B2System and method for filtering field programmable gate array input/output
Publication Date: 2019.04.02 ORACLE INT CORP
  • US10248585B2 patent drawing
  • US10248585B2 patent drawing
  • US10248585B2 patent drawing

AI summary

Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.