FPGA IO Periphery Time-Multiplexing With Partial Reconfiguration

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Solution Overview

Problem

Designing periphery devices for programmable circuits, such as FPGAs and ASICs, is challenging due to space constraints at the input/output periphery, where devices like memory controllers and UARTs require significant resources, making it difficult for EDA tools to optimize system design effectively.

Innovation Solution

Implementing partial reconfiguration (PR) to time-multiplex components in periphery devices, allowing for multiple instances of PR modules that can be dynamically reconfigured while static modules remain operational, thereby achieving area savings on the target device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If periphery devices are implemented on a target device, then functionality is improved, but area consumption increases

Engineering Contradiction:
ImprovefunctionalityVSAvoidarea consumption
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

Multiple periphery device instances are merged into a single shared physical location on the target device. The PR module serves as a common resource that is dynamically reconfigured to implement different periphery device instances (e.g., memory controller, DMA controller, UART) at the same physical location, thereby reducing overall area consumption while maintaining full functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The PR module implements dynamic reconfiguration capability, allowing the periphery device instance to be changed at runtime. This dynamic switching enables a single physical module to assume multiple functional roles depending on which periphery device instance is currently activated, resolving the contradiction between providing diverse functionality and minimizing area usage.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If multiple periphery device instances are supported, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improvemultiple instances supportVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The PR module is designed as a universal platform that can implement multiple different periphery device instances through reconfiguration. Rather than implementing separate dedicated hardware for each periphery device type, a single universal PR module handles all instances by loading appropriate configuration data, thereby supporting multiple instances without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The periphery device functionality is segmented into configurable components that can be independently instantiated. The PR module divides the implementation into a static framework and dynamically loadable instance-specific logic, allowing multiple instances to be supported through modular configuration rather than monolithic complex hardware.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If periphery devices are placed at IO periphery, then ease of operation is improved, but area availability worsens

Engineering Contradiction:
Improveease of operationVSAvoidarea availability
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

The solution transitions from spatial multiplexing (allocating separate physical areas for different periphery devices) to temporal multiplexing (sharing physical area across different time periods). By reconfiguring the PR module at different times to serve different periphery device instances, the system maintains ease of operation with proper IO periphery placement while dramatically improving area availability through time-based resource sharing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9384312B2Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration
Publication Date: 2016.07.05 ALTERA CORP
  • US9384312B2 patent drawing
  • US9384312B2 patent drawing
  • US9384312B2 patent drawing

AI summary

A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.