FPGA IQ Data Recording With Adaptive Lossless Compression

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Solution Overview

Problem

Spectrum analyzers face challenges in efficiently recording and analyzing high-bandwidth RF signals due to high data rate and memory requirements, limiting accurate analysis of wideband and multi-channel signals such as 5G and 6G.

Innovation Solution

Employing an FPGA-managed ADC subsystem with lossless data compression to reduce data transfer rate and memory needs, using multiple PCIe connections and USB/Flash memories for efficient IQ data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If wideband and multi-channel IQ data recording is implemented, then measurement capability is improved, but data rate and memory requirements increase

Engineering Contradiction:
Improvemeasurement capabilityVSAvoiddata rate and memory requirements
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential information from wideband IQ data by implementing lossless compression algorithms that identify and eliminate redundant data patterns. The FPGA-based compressor extracts statistical properties and temporal correlations from the IQ data stream, retaining only the critical information needed for accurate signal analysis while discarding redundant representations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter representation of IQ data by transforming time-domain samples into a compressed domain using statistical parameters and predictive models. The FPGA implements parameter-based encoding where consecutive samples are represented relative to previous values, and data is encoded using variable-length codes based on observed probability distributions, thereby reducing the bit rate while preserving measurement accuracy.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If higher data rate and internal memory are used, then wideband signal analysis is improved, but device size and cost increase

Engineering Contradiction:
Improvewideband signal analysisVSAvoiddevice size
Core Design Contradiction:
Measurement precisionVSVolume of stationary object

Solution Approach 1:

The patent replaces the mechanical approach of simply increasing memory capacity with a computational approach using lossless compression. Instead of provisioning sufficient memory to store all raw IQ data at full resolution, the system uses FPGA-based compression algorithms that mathematically reduce the data volume while preserving all information needed for accurate wideband signal analysis, thereby reducing memory hardware requirements and device size.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Quantity of substance

If lossless compression is implemented, then data storage efficiency is improved, but processing complexity increases

Engineering Contradiction:
Improvedata storage efficiencyVSAvoidprocessing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements self-service compression where the compression algorithm adapts automatically to the statistical properties of the input IQ data without requiring external configuration or intervention. The FPGA-based compressor continuously learns the data distribution characteristics and adjusts its encoding parameters in real-time, performing both compression and adaptation autonomously within the data path, thereby managing processing complexity through self-optimization rather than external control.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12512847B2Wideband and multi-channel real-time IQ data recording with FPGA-based lossless compression
Publication Date: 2025.12.30 VIAVI SOLUTIONS INC(US)
  • US12512847B2 patent drawing
  • US12512847B2 patent drawing
  • US12512847B2 patent drawing

AI summary

Field programmable gate array (FPGA) based lossless data compression may be used in a test device such as a spectrum analyzer to efficiently reduce the data transfer rate and needed memory. Multi-channel IQ data may be flexibly recorded using multiple lanes of high data rate connections such as JESD204B/C and PCIe between an analog-digital-converter (ADC), the FPGA, and a processor. Bandwidth, sample rate, and/or bit number may determine the IQ data size. When the IQ data size is less than a product of the compression coefficient and the data transfer rate, the lossless compression may be skipped saving logic usage and power consumption in FPGA. Thus, depending on memory and transfer rate perspectives, a decision may be made whether the compression needs to be used or not.