FPGA Ising Optimization Control for Variable Scale and Precision

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing optimization devices are inefficient as they require individual manufacturing for each problem, with varying numbers of spin bits and weight coefficients, making it difficult to adapt to different scales and precisions.

Innovation Solution

An optimization device with a field programmable gate array (FPGA) implementation that allows dynamic adjustment of the number of spin bits and weight coefficients, enabling flexible scaling and precision based on the problem at hand.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a large number of design variables are handled to achieve comprehensive optimization, then optimization precision is improved, but computational time and resource consumption increase significantly

Engineering Contradiction:
Improveoptimization precisionVSAvoidcomputational time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent divides the complete set of design variables into multiple groups based on their importance and characteristics. Different optimization strategies are applied to different groups: some variables are optimized with high precision while others are handled with coarser granularity, thereby reducing overall computational time while maintaining acceptable optimization precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different optimization methods and precision levels to different design variables based on their local characteristics. Critical variables requiring high precision are handled with more computationally intensive methods, while less critical variables are optimized using faster, less precise methods, thus balancing overall optimization quality with computational efficiency.

Inventive Principle:
Principle #3Local quality

2Productivity

If multiple optimization methods are combined to handle different design variables, then optimization effectiveness is improved, but device complexity increases

Engineering Contradiction:
Improveoptimization effectivenessVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a unified optimization device that can handle multiple types of design variables using a common framework. The device incorporates multiple optimization methods within a single integrated system, allowing it to switch between different methods based on the variable type rather than requiring separate specialized devices for each variable category.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces an intermediary layer that manages the complexity of coordinating multiple optimization methods. This intermediary component automatically selects and switches between different optimization methods based on the design variable characteristics, shielding the user from the complexity of method selection and coordination while maintaining optimization effectiveness.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3852028B1Optimization device, control method for optimization device, and control program for optimization device
Publication Date: 2026.04.29 FUJITSU LTD
  • EP3852028B1 patent drawingFigure 1
  • EP3852028B1 patent drawingFigure 2
  • EP3852028B1 patent drawingFigure 3

AI summary

To make scale and precision variable. A storage unit (11) stores a coefficient indicating magnitude of an interaction between bits in a spin bit string representing a state of an Ising model. When any bit in the spin bit string is inverted, each of bit operation circuits (1a1 to 1aN) outputs a signal indicating inversion availability of an own bit according to energy change calculation using the coefficient corresponding to the inverted bit and the own bit read from the storage unit. A selection circuit unit (2) outputs a signal indicating a bit to be inverted selected on the basis of the signal indicating inversion availability output from each of the bit operation circuits (1a1 to 1aK) of the first number of bits (K) of the spin bit string to each of the bit operation circuits (1a1 to 1aK). A setting change unit (5) changes the first number of bits (K) for the selection circuit unit (2) and changes the second number of bits of the coefficients for the bit operation circuits (1a1 to 1aK).