FPGA Component Isolation and Data Encryption for Secure Computing

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Solution Overview

Problem

Field programmable gate arrays (FPGAs) used in general-purpose computing systems are susceptible to security breaches, as data transfers and memory inspections can reveal cryptographic keys and secure operation information, necessitating enhanced security measures.

Innovation Solution

Implementing encryption and digital signing of data and code transferred between the FPGA and other system components, using cryptographic keys, and isolating FPGA components to protect against unauthorized access and ensure secure operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FPGA components are isolated to protect against security breaches, then security is improved, but device complexity increases

Engineering Contradiction:
ImprovesecurityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The FPGA device is divided into multiple isolated components including separate memory regions, processing regions, and I/O regions. Each region has controlled access permissions, creating security boundaries that prevent unauthorized access while maintaining functional separation. This segmentation approach improves security by limiting the attack surface and preventing lateral movement of threats within the device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A memory management unit acts as an intermediary component between the CPU and FPGA memory regions. This mediator enforces access control policies, managing permissions for reading and writing operations. The intermediary layer provides security enforcement without requiring complex changes to the underlying FPGA architecture, thus improving security while managing complexity through a dedicated control component.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If data and code are encrypted and digitally signed, then security is improved, but processing time increases

Engineering Contradiction:
ImprovesecurityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Code and data are encrypted and digitally signed in advance before being loaded into the FPGA. The encryption and digital signing operations are performed during the compilation or deployment phase, not during runtime execution. This preliminary action ensures security validation occurs before the FPGA operates, avoiding time penalties during actual processing operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The FPGA device performs self-authentication by verifying digital signatures on its own configuration code and data using cryptographic modules integrated within the device. This self-service approach to security verification eliminates the need for external authentication operations during runtime, maintaining processing speed while ensuring security through internal cryptographic validation.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9230091B2Managing use of a field programmable gate array with isolated components
Publication Date: 2016.01.05 MICROSOFT TECHNOLOGY LICENSING LLC
  • US9230091B2 patent drawing
  • US9230091B2 patent drawing
  • US9230091B2 patent drawing

AI summary

Field programmable gate arrays can be used as a shared programmable co-processor resource in a general purpose computing system. Components of an FPGA are isolated to protect the FPGA and data transferred between the FPGA and other components of the computer system. For example, data written by the FPGA to memory is encrypted, and is decrypted within the FPGA when read back from memory. Data transferred between the FPGA and other components such as the CPU or GPU, whether directly or through memory, can similarly be encrypted using cryptographic keys known to the communicating components. Transferred data also can be digitally signed by the FPGA or other component to provide authentication. Code for programming the FPGA can be encrypted and signed by the author, loaded into the FPGA in an encrypted state, and then decrypted and authenticated by the FPGA itself, before programming the FPGA with the code.