Jitter Modeling for FPGA Timing Analysis
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Solution Overview
Problem
Current timing analysis methods fail to accurately model jitter effects in complex systems, particularly in field programmable gate arrays (FPGAs), leading to reduced timing margins and increased cycle-to-cycle delay variation due to sensitive transistor responses to supply voltage changes.
Innovation Solution
A method for modeling jitter that accounts for delay-impacting parameters such as voltage and temperature, generating delay per element functions, and identifying differences in path delays to estimate jitter accumulation, especially for signals broadcast off-chip or received from off-chip, and its impact on data transfers within a device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor threshold voltages are reduced to increase performance, then speed is improved, but timing stability deteriorates due to increased sensitivity to supply voltage changes
Solution Approach 1:
The patent changes the parameter of transistor threshold voltage to achieve higher performance speeds. By reducing the threshold voltage, transistors switch faster, improving overall system speed. However, this creates increased sensitivity to supply voltage variations, which is managed through jitter modeling that accounts for these parameter changes and their impact on timing stability.
2Use of energy by moving object
If supply voltage is reduced to decrease power consumption, then energy use is improved, but manufacturing precision deteriorates due to increased delay variation
Solution Approach 1:
The patent reduces the supply voltage parameter to lower power consumption in high-performance devices. This parameter change inevitably increases gate and buffer delay variations. The invention compensates for this by implementing jitter modeling that captures the relationship between supply voltage, delay variation, and timing margins, allowing designers to account for these precision changes in their timing analysis.
3Reliability
If timing analysis includes jitter modeling, then reliability is improved, but device complexity increases due to additional analysis requirements
Solution Approach 1:
The patent implements jitter modeling as a preliminary action in the timing analysis process. By pre-characterizing jitter effects and incorporating them into the timing analysis framework before final design validation, the invention improves timing reliability without requiring complex real-time analysis. The jitter models are prepared in advance based on device characteristics and supply voltage conditions, streamlining the overall analysis complexity.
Data Source
AI summary
A method for modeling jitter includes generating a first delay-impacting parameter function for a first signal and a second delay-impacting parameter function for a second signal. A first delay per element function is generated from the first delay-impacting parameter function and a second delay per element function from the second delay-impacting parameter function. A difference in path delay from the first delay per element function and the second delay per element function is identified.