FPGA Output Lane Training for SFI-5 Inter-Lane Alignment
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Solution Overview
Problem
Current Field Programmable Gate Arrays (FPGAs) are unable to achieve the required inter-lane alignment of 5 unit intervals as specified by the SERDES Framer Interface (SFI-5) standard, leading to challenges in aligning multiple data lanes in optical interfaces.
Innovation Solution
A method where each data lane is trained independently by transmitting a short fixed pattern on unaligned lanes to mask their out-of-alignment nature, followed by adjusting the preskew value on the aligned lane until the receiving component indicates acceptable skew, allowing for precise alignment within the SFI-5 standard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a short fixed pattern is transmitted on unaligned lanes to mask their out-of-alignment nature, then the receiving component can lock onto the pattern within capture range, but the lanes remain out of alignment requiring additional training steps
Solution Approach 1:
The patent applies preliminary action by first transmitting a short fixed pattern on all lanes before independent lane training. This preliminary step allows the receiving component to lock onto patterns within its capture range, establishing a baseline state before the more complex independent training process begins. The short pattern transmission prepares the system by ensuring all lanes are at least partially synchronized, making subsequent alignment adjustments more effective.
2Manufacturing precision
If independent lane training is implemented to achieve 5 unit interval alignment, then alignment precision meets SFI-5 standard, but the training process becomes more complex compared to conventional approaches
Solution Approach 1:
The patent applies segmentation by dividing the alignment process into independent lane training steps. Each data lane is trained separately with individual preskew value adjustments, rather than attempting to align all lanes simultaneously. This segmentation allows precise control over each lane's alignment status and enables the system to meet the stringent 5 unit interval SFI-5 standard through methodical, lane-by-lane optimization.
Solution Approach 2:
The patent applies parameter changes by systematically adjusting the preskew value parameter for each data lane during independent training. The preskew value is modified in controlled increments to achieve the desired alignment precision. This parameter adjustment approach allows fine-tuning of each lane's timing characteristics to meet the tight alignment requirements while providing a structured method to manage the increased training complexity.
3Manufacturing precision
If preskew values are adjusted in small increments to find optimal alignment, then alignment accuracy improves, but training time increases
Solution Approach 1:
The patent applies dynamics by implementing an adaptive training process that adjusts the increment size based on alignment progress. The system dynamically modifies the preskew adjustment strategy, using larger increments when far from optimal alignment and smaller increments when approaching the target alignment state. This dynamic approach optimizes the balance between training time and alignment accuracy, avoiding unnecessarily fine adjustments when coarse alignment is sufficient.
Data Source
AI summary
Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.