FPGA Learning Device for Decision Tree Parallel Processing

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Solution Overview

Problem

Current machine learning technologies, particularly gradient boosting decision trees (GBDT), face challenges in processing speed and accuracy when handling large datasets, especially for image and voice data, due to limitations in address calculation and memory access latency, which hinders real-time performance in applications like robotics and high-frequency trading.

Innovation Solution

A learning device is configured with multiple learning units and managers to perform parallel learning processing by calculating addresses for decision tree nodes, utilizing a field-programmable gate array (FPGA) to enhance processing speed through Feature Parallel and Data Parallel techniques, optimizing memory access and reducing calculation time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If learning processing is performed in parallel by dividing learning data into pieces, then processing speed is improved, but address calculation time increases

Engineering Contradiction:
Improveprocessing speedVSAvoidaddress calculation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the learning data into multiple pieces and assigns different learning units to process different segments in parallel. Each learning unit is responsible for a specific portion of the data, enabling simultaneous processing across multiple units while maintaining organized address management for each segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a manager component that acts as an intermediary between the parallel learning units and the memory system. The manager handles address calculation and coordination, reducing the burden on individual learning units and optimizing the overall address management efficiency in the parallel processing architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If gradient boosting is used for structured data, then processing speed is improved compared to deep learning, but accuracy is reduced for image, voice, and language data

Engineering Contradiction:
Improveprocessing speedVSAvoidaccuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent modifies the gradient boosting algorithm by changing key parameters such as introducing regularization terms, adjusting learning rates, and optimizing tree construction parameters. These parameter changes enable the algorithm to achieve better accuracy on unstructured data like images, voice, and language while preserving the processing speed advantages of gradient boosting.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11645573B2Learning device and learning method
Publication Date: 2023.05.09 RICOH CO LTD
  • US11645573B2 patent drawing
  • US11645573B2 patent drawing
  • US11645573B2 patent drawing

AI summary

A learning device is configured to perform learning of a decision tree, and includes: a plurality of learning units each corresponding to a data memory of a plurality of data memories, and being configured to perform learning at a first node using learning data acquired by using first addresses related to a storage destination of the learning data corresponding to the first node of the decision tree in the data memory, and output a second address related to a storage destination of each piece of the learning data branched from the first node; and a plurality of managers each corresponding to a learning unit of the plurality of learning units, and being configured to calculate third addresses related to storage destinations of learning data corresponding to second nodes being next nodes of the first node using the first addresses and the second address output from the learning unit.