Synchronous LED Control via FPGA Register Bundling
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Solution Overview
Problem
Existing information processing systems face challenges in synchronizing control signals across multiple server modules connected via SMP connections, leading to complex wiring and inefficiencies, especially when dealing with strong data dependency and time-sensitive operations.
Innovation Solution
The implementation of a synchronous control mechanism using FPGAs with synchronous registers and internode communication access control units that transmit and receive packets at predetermined intervals to synchronize control signals across information processing devices, reducing the need for complex wiring and ensuring timely data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control signals are transmitted via traditional wiring methods between multiple server modules, then the system can operate, but the wiring becomes complicated and synchronization time increases
Solution Approach 1:
The patent combines multiple control signals into a single bundled signal transmitted through the SMP connection interface. Instead of using separate wiring for each control signal between server modules, the invention merges these signals into one communication channel, thereby reducing wiring complexity while maintaining reliable synchronization.
Solution Approach 2:
The patent introduces an intermediary mechanism (the SMP connection interface with bundled control signals) that mediates between multiple server modules. This intermediary allows control signals to be transmitted efficiently without requiring direct complex wiring between each module pair, thus simplifying the overall system architecture.
2Reliability
If control signals are synchronized using existing SMP connection methods, then some synchronization is achieved, but synchronization time is not ensured for time-sensitive operations
Solution Approach 1:
The patent implements preliminary action by pre-bundling control signals into the SMP connection interface before transmission. This preparation ensures that when time-sensitive operations require synchronization, the control signals are already organized and ready for immediate transmission, minimizing synchronization time and ensuring deterministic performance.
Solution Approach 2:
The patent employs periodic action through the use of bundled control signals transmitted at regular intervals via the SMP connection. This periodic transmission ensures that time-sensitive operations receive synchronized control signals within predictable time frames, meeting deterministic timing requirements.
3Adaptability or versatility
If multiple control signals are transmitted separately between server modules, then each signal can be controlled independently, but the number of control signals and wiring topology become complex
Solution Approach 1:
The patent merges multiple independently controllable signals into a single bundled transmission channel through the SMP interface. This merging maintains the independence of each control signal logically while physically combining them into one wiring path, thereby preserving adaptability while reducing wiring complexity.
Solution Approach 2:
The SMP connection interface serves multiple functions: it transmits data, control signals, and synchronization information through a single universal channel. This multi-functionality allows the system to maintain independent control of various signals while using a unified wiring topology, reducing overall system complexity.
Data Source
AI summary
In an information processing system, plural information processing devices are mutually connected by an SMP connection mechanism. Each of the information processing devices includes a control device (FPGA) having a synchronous register that shows the state of a control signal of the information processing device and an internode communication access control unit that transmits first synchronous packets with the content of the synchronous register reflected to the other information processing devices at predetermined time intervals, receives second synchronous packets from the other information processing devices, and reflects the content of the received second synchronous packets on the synchronous register.


