Three-Stage FPGA Level Conversion Circuit for High-Voltage Word-Line Drive
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Solution Overview
Problem
Flash FPGAs require high voltage for programming and erasure, necessitating a level conversion circuit to convert low core voltage to high voltages, and their flash cell arrays have large word and bit lines, demanding a high driving force and speed in the level conversion circuit.
Innovation Solution
A logic process-based level conversion circuit with cascaded first-stage, intermediate-stage, and drive-stage conversion modules, utilizing voltage dividing switch transistors and differential signal structures to achieve efficient voltage conversion and reduce device working time under break-down voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single-stage level conversion circuit is used to convert low voltage to high voltage, then the conversion speed may be fast, but the driving force is insufficient for large word lines and bit lines
Solution Approach 1:
The level conversion circuit is divided into three stages: first-stage conversion module, intermediate-stage conversion module, and drive-stage conversion module. Each stage handles a portion of the voltage conversion task, with the first stage converting VDD-GND to VP1-GND, the intermediate stage converting VP1-GND to VP1-VN, and the drive stage converting VP1-VN to VP2-VN. This segmentation allows each module to provide sufficient driving force while managing complexity through modular design.
2Power
If the word line and bit line are made large in size to ensure driving capability, then the driving force is sufficient, but the load increases and requires higher conversion speed
Solution Approach 1:
The three-stage conversion structure distributes the driving burden across multiple modules. The drive-stage conversion module specifically handles the final high-voltage output with sufficient driving capability, while previous stages prepare signals with appropriate timing. This allows the use of larger word lines and bit lines without compromising conversion speed, as each stage operates optimally within its voltage domain.
Solution Approach 2:
The first-stage and intermediate-stage conversion modules perform preliminary voltage conversion and signal preparation before the final drive stage. This preliminary action ensures that the drive-stage module receives pre-conditioned signals, allowing it to focus on providing high driving capability to the large word lines and bit lines without being bottlenecked by previous stages.
3Productivity
If high voltage is applied to erase and program flash cells, then the programming and erasure functions are achieved, but devices cannot work under break-down voltage for extended periods
Solution Approach 1:
The level conversion circuit operates in periodic cycles, switching between maintenance phase and programming/erasure phases. During the maintenance phase, voltage dividing switch transistors are turned off and parasitic capacitors maintain the voltage levels. During programming/erasure phases, high voltage is applied briefly through the drive-stage module. This periodic operation allows high voltage to be applied only when needed for short durations, achieving programming and erasure capabilities while minimizing exposure time that would compromise device reliability.
Solution Approach 2:
The circuit rushes through the high-voltage programming and erasure operations as quickly as possible using the drive-stage conversion module, then immediately transitions to the maintenance phase where voltage dividing switch transistors are turned off. This minimizes the time devices spend under break-down voltage conditions, allowing the system to achieve necessary programming and erasure functionality while protecting device reliability by limiting exposure to high-stress conditions.
4Adaptability or versatility
If voltage dividing switch transistors are used for voltage division, then the voltage conversion is achieved, but the devices work under break-down voltage which reduces reliability
Solution Approach 1:
Voltage dividing switch transistors are activated only during programming and erasure phases when high voltage conversion is needed, and turned off during maintenance phases. This periodic activation allows the circuit to achieve necessary voltage conversion adaptability while limiting the duration that devices operate under break-down voltage conditions, thereby preserving reliability.
Solution Approach 2:
The voltage dividing switch transistors are used only briefly to perform the necessary voltage division for programming and erasure operations, then the circuit skips to the maintenance phase where these transistors are turned off. This approach achieves the required voltage conversion capability while minimizing the time devices spend in the high-stress break-down region, thus maintaining reliability.
Data Source
AI summary
A logic process-based level conversion circuit of a flash flash field programmable gate array (FPGA) performs three-stage level conversion by using three conversion modules. A first-stage conversion module is configured to convert an input first signal of a VDD-GND voltage domain into a second signal of a VP1-GND voltage domain, an intermediate-stage conversion module is configured to convert the input second signal of the VP1-GND voltage domain into a third signal of a VP1-VN voltage domain, and a drive-stage conversion module is configured to convert the input third signal of the VP1-VN voltage domain into a drive signal of a VP2-VN voltage domain and output a drive word line. The logic process-based level conversion circuit reduces the pressure of conversion at each stage, ensures a capability of driving the next stage, increases the conversion speed, and provides a large driving capability at the last stage.