FPGA Link Budget Synchronization for Deterministic Packet Loss Simulation

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Solution Overview

Problem

Current software-based modeling tools for computing and communication hardware development are limited by their inability to handle high-speed data rates and are non-deterministic, leading to inefficiencies and substandard design iterations, which result in high costs and extended development times.

Innovation Solution

The use of custom hardware, such as Field Programmable Gate Arrays (FPGA), Very High Speed Integrated Circuit (VHSIC), and Complex Programmable Logic Device (CPLD) hardware to model high-speed communication systems, providing deterministic outputs and handling high data rates by simulating latency, jitter, and losses directly at the hardware level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If software-based modeling tools are used, then ease of operation and flexibility are improved, but data rate handling capability and determinism deteriorate

Engineering Contradiction:

Improveease of operationVSAvoiddata rate handling capability

Core Design Contradiction:

Ease of operationVSSpeed

Solution Approach 1:

The patent introduces hardware acceleration as an intermediary component that bridges software modeling tools and high-speed data processing requirements. The hardware accelerator handles time-critical data rate processing while the software maintains ease of operation for system configuration and control, resolving the contradiction between operational flexibility and data rate handling capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system is segmented into software-based modeling components for high-level control and hardware acceleration components for low-level data processing. This segmentation allows each component to optimize for its specific function, with software providing ease of operation and hardware providing high-speed data rate handling.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If software-based modeling tools are used, then adaptability is improved, but determinism and simulation accuracy deteriorate

Engineering Contradiction:

ImproveadaptabilityVSAvoiddeterminism

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

Hardware acceleration serves as an intermediary that ensures deterministic behavior for time-critical operations while software maintains adaptability for configuration. The hardware component provides consistent, predictable performance for data processing, eliminating the non-determinism inherent in pure software solutions.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If multiple hardware iterations are performed, then manufacturing precision and design quality are improved, but development time and cost increase

Engineering Contradiction:

Improvedesign qualityVSAvoiddevelopment time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent creates a hardware accelerator that can be rapidly reconfigured through software programming rather than requiring physical fabrication for each design iteration. This allows multiple design versions to be tested using the same hardware platform, significantly reducing development time while maintaining manufacturing precision through hardware-based simulation accuracy.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The hardware accelerator is designed with programmable functionality that allows design iterations to be performed before final hardware fabrication. By preliminarily testing and validating designs using the reconfigurable hardware platform, the system reduces the need for multiple expensive hardware fabrications, thereby reducing both time and cost.

Inventive Principle:

Principle #10Preliminary action

4Ease of operation

If event schedulers are used in software systems, then coordination capability is improved, but processing speed and capacity deteriorate

Engineering Contradiction:

Improvecoordination capabilityVSAvoidsimulation capacity

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent replaces software-based event scheduling mechanisms with hardware-based time synchronization and coordination. The hardware accelerator handles time-critical coordination operations directly at the hardware level, eliminating the performance bottleneck of software event schedulers while maintaining precise coordination capability through hardware clocks and counters.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11683239B2Synchronizing dynamic link budgets with FPGA based simulation waveform state machines

Publication Date: 2023.06.20 L3HARRIS TECH INC

AI summary

A system for simulating lost data packets. The system includes a first hardware register storing data for fast factors. The fast factors include factors that are time independent with respect to particular data packets. A second hardware register stores slow factors. The slow factors include factors that are time dependent on data packets. Synchronization hardware is coupled to the second hardware register and synchronizes the slow factors with specific data inputs based on dependencies on the data packets. A hardware adder is coupled to the first hardware register and the second hardware register to compute a link budget. The link budget is used in determine probability of loss of data packets. A hardware processor coupled to the hardware adder determines, based on the link budget, if a data packet should be dropped, and when the data packet should be dropped, drops the data packet for simulating a network physical layer.