FPGA Logic Cells With Direct LUT-to-Adder Arithmetic Packing
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) have limited arithmetic density due to insufficient number of adders and excessive routing circuitry, making them less competitive with other computing devices like graphics processing units and application-specific standard products.
Innovation Solution
Incorporating logic cells with more than two full adder circuits, such as at least three or four full adders, along with 4-input lookup tables decomposed into 3-input LUTs, to enhance arithmetic density and support binary, ternary, or quaternary additions and multiplications efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional adaptive logic modules include only one or two adders, then device complexity is reduced, but arithmetic density is limited
Solution Approach 1:
The patent combines multiple adder circuits (at least three full adders) within a single adaptive logic module, merging arithmetic functions that were previously distributed across multiple modules. This consolidation increases arithmetic density by integrating more computational resources into a unified structure, resolving the contradiction between quantity of arithmetic operations and device complexity.
2Quantity of substance
If conventional PLDs include disproportionate routing circuitry, then adaptability is improved, but arithmetic density deteriorates
Solution Approach 1:
The patent implements local quality by providing direct connection paths between lookup table outputs and adder inputs within the same logic module, creating optimized local routing for arithmetic operations. This localized direct connectivity enhances arithmetic density without compromising overall adaptability, as the routing structure is tailored specifically for computational efficiency while maintaining general programmability through configurable logic elements.
3Quantity of substance
If more full adder circuits are incorporated into logic cells, then arithmetic density increases, but manufacturing cost increases
Solution Approach 1:
The patent achieves universality by designing logic modules where the same structural framework supports multiple arithmetic operations (binary addition, ternary addition, quaternary addition, multiplication) using the same full adder circuits and lookup tables. This multi-functional design increases arithmetic density without proportionally increasing manufacturing cost, as the same hardware resources serve multiple computational purposes through configurable connections and operations.
Data Source
AI summary
Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.