FPGA Logic Cell Carry Architecture for 3:2 Compressors
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Solution Overview
Problem
Existing FPGA logic cell architectures require excessive connections to the programmable routing network to implement 3:2 compressors, leading to increased power consumption and complexity, which is undesirable for cost-effective and efficient FPGA designs.
Innovation Solution
A logic cell architecture featuring K-input lookup table circuitry with shared inputs between two (K−1)-input LUTs, multiplexers, and an exclusive-OR gate to generate sum and carry-out outputs independently of primary outputs, reducing the need for connections to the programmable routing network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single logic cell is used to implement a 3:2 compressor, then the number of logic cells required is reduced, but the number of connections to the programmable routing network increases
Solution Approach 1:
The logic cell is segmented into distinct functional blocks: LUT circuitry for computing primary outputs, carry circuitry for computing sum and carry-out, and multiplexer circuitry for selecting outputs. This segmentation allows each block to be optimized independently, reducing the need for excessive routing connections while maintaining compressor functionality.
Solution Approach 2:
The logic cell is designed as a multi-functional unit that can simultaneously compute primary outputs, sum outputs, and carry-out outputs. The carry circuitry can be configured to generate sum outputs independently of primary outputs, enabling the cell to function as a complete 3:2 compressor within a single cell structure.
2Adaptability or versatility
If more inputs and outputs are connected to the programmable routing network, then the versatility of the logic cell increases, but the complexity and cost of the FPGA increases
Solution Approach 1:
The logic cell employs configurable multiplexers that can dynamically select between different output sources (primary outputs from LUTs, sum outputs from carry circuitry, or carry-out outputs). This dynamic configurability allows the cell to adapt to different functional requirements without requiring dedicated physical connections for each possible function, reducing overall FPGA complexity.
Solution Approach 2:
Multiplexer circuitry serves as an intermediary between the internal logic blocks (LUTs and carry circuitry) and the programmable routing network. The multiplexers consolidate multiple potential output signals into a limited number of routed outputs, reducing the number of direct connections required to the routing network while maintaining full functional versatility.
3Ease of manufacture
If traditional logic cell architectures are used to implement compressors, then implementation is straightforward, but power consumption and complexity increase
Solution Approach 1:
The invention merges the functionality of multiple traditional logic cells into a single optimized logic cell structure. The carry circuitry is integrated directly with the LUT outputs through multiplexers, allowing the cell to implement compressor functions (sum and carry-out generation) without requiring separate dedicated cells for each output, thereby reducing power consumption while maintaining ease of implementation.
Data Source
AI summary
A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).