3D FPGA Logic Disaggregation for Shorter Critical Paths
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Solution Overview
Problem
The performance of programmable integrated circuits, such as FPGAs, is limited by long signal propagation delays through combinational logic paths that traverse memory and specialized processing blocks.
Innovation Solution
A disaggregated architecture is implemented, where logic circuitry is formed in a first integrated circuit die and memory and specialized processing blocks are formed in a second die, stacked on top of the first. This configuration reduces capacitive loading and eliminates feedthrough paths, thereby lowering interconnect latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If logic circuitry, memory blocks, and specialized processing blocks are integrated on a single die, then device complexity is reduced and routing is simplified, but signal propagation delay increases and performance is limited
Solution Approach 1:
The patent divides the programmable logic device into multiple separate dies: a first die containing logic array blocks and a second die containing memory blocks and specialized processing blocks. This segmentation allows each die to be optimized independently, reducing signal propagation delays within logic paths while maintaining the functional integration benefits through vertical stacking and inter-die routing.
2Productivity
If memory blocks and specialized processing blocks are placed in the path between logic array blocks, then functional integration is improved, but interconnect latency and power consumption increase
Solution Approach 1:
The patent extracts memory blocks and specialized processing blocks from the horizontal routing paths between logic array blocks and relocates them to a separate second die. This extraction eliminates feedthrough paths where signals would unnecessarily traverse memory or DSP blocks, reducing interconnect latency and power consumption while maintaining functional integration through the stacked architecture.
3Speed
If a single die architecture is used, then manufacturing is simplified, but the longest combinational logic path sets a critical path that limits performance
Solution Approach 1:
The patent transitions from a two-dimensional single-die layout to a three-dimensional stacked architecture. By stacking the logic array die and the memory/DSP die vertically and using through-silicon vias for interconnection, the patent achieves shorter critical paths and improved performance while managing manufacturing complexity through established 3D integration techniques.
Data Source
AI summary
A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.