Commodity FPGA Logic Drive for Low-Cost Advanced Node Development
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Solution Overview
Problem
The transition from Field Programmable Gate Arrays (FPGA) to Application Specific Integrated Circuits (ASIC) or Customer-Owned Tooling (COT) chips is hindered by higher power consumption, larger chip size, lower performance, and significantly increased Non-Recurring Engineering (NRE) costs as semiconductor technology nodes advance, limiting innovation and making it costly to implement advanced technology nodes.
Innovation Solution
A standardized commodity logic drive utilizing plural FPGA IC chips and non-volatile memory IC chips, allowing for field programming and reducing NRE costs by enabling innovators to develop and implement algorithms and applications using advanced technology nodes without the high costs associated with ASIC or COT chip design, by using software to program the logic drive.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability and ease of operation are improved, but power consumption increases, chip size increases, performance decreases, and fabrication cost increases
Solution Approach 1:
The system divides the computing workload into two segments: training phase using FPGA-based logic drives for adaptability, and inference phase using optimized ASIC/GPU for performance. This segmentation allows each component to operate in its optimal mode, reducing overall power consumption while maintaining field programming capability during training.
Solution Approach 2:
The system dynamically switches between FPGA-based logic drives and ASIC/GPU based on the operational phase (training vs. inference). During training, the FPGA provides reconfigurability; during inference, the system transitions to more power-efficient hardware, optimizing power consumption across different operational states.
2Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability is improved, but chip size increases and fabrication yield decreases
Solution Approach 1:
The system segments the computational tasks, using compact FPGA logic drives only for training where reconfigurability is essential. The larger, more specialized ASIC/GPU handles inference tasks, allowing the FPGA chip size to be minimized while maintaining necessary adaptability for field programming during training phases.
3Power
If ASIC or COT chip design is used to expand application volume, then performance and power efficiency are improved, but NRE cost increases significantly
Solution Approach 1:
The system performs preliminary training using FPGA-based logic drives before deploying to ASIC/GPU for inference. This preliminary action allows the model to be developed and validated using reconfigurable hardware with lower NRE costs, and only then transitions to the more expensive but efficient ASIC/GPU implementation, reducing overall manufacturing barriers.
Solution Approach 2:
The FPGA-based logic drive serves as an intermediary between the development phase and the final ASIC/GPU deployment. It allows innovators to prototype and train models with lower NRE costs, acting as a bridge that reduces the barrier to entry before committing to expensive ASIC manufacturing.
4Power
If advanced semiconductor technology nodes are used, then performance and power efficiency are improved, but NRE cost increases greatly
Solution Approach 1:
The system performs preliminary development and training using FPGA logic drives fabricated at less advanced, lower-cost nodes. Only after validation does it transition to advanced technology nodes for final deployment, allowing performance optimization without immediately incurring the high NRE costs of advanced node manufacturing.
Solution Approach 2:
FPGA-based logic drives serve as an intermediary platform that enables innovators to develop algorithms and models using standard commodity chips at lower cost nodes. This intermediary approach reduces the barrier to using advanced technology nodes by allowing preliminary work to be done on cheaper, more accessible hardware.
Data Source
AI summary
A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.