Commodity FPGA Logic Drive With NVM to Cut ASIC NRE Costs
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Solution Overview
Problem
The high cost and inefficiencies of transitioning from Field Programmable Gate Arrays (FPGA) to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips for semiconductor applications, particularly in advanced technology nodes, hinder innovation and scalability due to larger chip size, higher fabrication costs, and increased Non-Recurring Engineering (NRE) expenses.
Innovation Solution
Employing a standardized commodity logic drive comprising plural FPGA IC chips and non-volatile memory IC chips, which reduces NRE costs by enabling field programming for various applications, allowing developers to use software to implement innovations without the high costs associated with ASIC or COT chip design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for semiconductor applications, then adaptability and ease of operation are improved, but chip size, fabrication cost, and power consumption increase
Solution Approach 1:
The system is divided into two separate components: a commodity FPGA-based logic drive that provides adaptability and an ASIC-based storage drive that provides high-density data storage. This segmentation allows each component to be optimized for its specific function, reducing the overall chip size required while maintaining adaptability through the FPGA portion.
Solution Approach 2:
The logic drive using commodity FPGA IC chips serves as a universal platform that can be programmed to perform various logic functions and applications. This multi-functionality provides adaptability without requiring custom ASIC design for each application, thereby reducing chip size and fabrication costs compared to application-specific implementations.
2Adaptability or versatility
If FPGA IC chips are used for semiconductor applications, then adaptability is improved, but fabrication cost increases
Solution Approach 1:
The system uses commodity FPGA IC chips that are relatively inexpensive and can be programmed and reprogrammed multiple times. This approach replaces expensive custom ASIC fabrication with affordable, off-the-shelf FPGA components, significantly reducing fabrication costs while maintaining adaptability through software programming.
Solution Approach 2:
Instead of changing the physical fabrication parameters through custom ASIC design, the system changes the logical parameters through FPGA programming. This allows adaptability to be achieved through software configuration rather than expensive hardware re-fabrication, reducing manufacturing costs while maintaining versatility.
3Productivity
If advanced technology nodes are used for ASIC or COT chip design, then performance is improved, but NRE cost increases greatly
Solution Approach 1:
The system uses commodity FPGA IC chips that replicate the functionality of expensive custom ASIC designs through programming. Instead of investing millions in NRE costs for custom chip fabrication, developers can copy desired logic functions through FPGA configuration files, achieving similar performance at a fraction of the cost.
Solution Approach 2:
The FPGA chips are pre-configured with desired logic functions through programming before deployment. This preliminary action allows the system to achieve high performance comparable to ASICs without incurring the high NRE costs, as the configuration can be done through software rather than expensive mask fabrication processes.
Data Source
AI summary
A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.