FPGA Logic Drive Using Non-Volatile LUT Memory to Cut NRE Cost
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Solution Overview
Problem
The high cost and complexity of transitioning from Field Programmable Gate Array (FPGA) IC chips to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips, particularly in advanced semiconductor technology nodes, hinder innovation and scalability due to increased Non-Recurring Engineering (NRE) costs and performance limitations.
Innovation Solution
Utilizing standardized commodity FPGA IC chips in a multi-chip package for logic drives, enabling field programming to reduce NRE costs and facilitate innovation, allowing developers to implement advanced semiconductor technology nodes like 16 nm, 10 nm, 7 nm, or 5 nm with reduced costs and increased accessibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transitioning from FPGA IC chips to ASIC or COT chips is performed to improve performance and reduce power consumption, then device performance and energy efficiency are improved, but Non-Recurring Engineering (NRE) costs and device complexity increase significantly
Solution Approach 1:
The patent applies universality by using standardized commodity FPGA IC chips that can be field-programmed to perform multiple different logic functions and applications. A single FPGA chip design serves as a universal platform that can be reconfigured for various applications through field programming, eliminating the need for separate ASIC designs for each application while achieving performance and power efficiency comparable to application-specific implementations
Solution Approach 2:
The patent applies dynamics through field-programmable logic that can be reconfigured after manufacturing. The FPGA chips allow dynamic changes in logic functionality through configuration memory cells that can be programmed in the field, enabling the same hardware platform to adapt to different performance and power requirements for various applications without requiring new manufacturing processes
2Speed
If migrating to advanced semiconductor technology nodes is performed to improve performance, then device performance is improved, but NRE costs increase greatly
Solution Approach 1:
The patent applies copying by using standardized commodity FPGA IC chip designs that can be replicated and deployed across multiple technology nodes. The same logic design can be implemented on FPGAs manufactured at different technology nodes (16 nm, 10 nm, 7 nm, 5 nm) without requiring redesign, allowing performance scaling with technology node advancement while avoiding the high NRE costs of custom ASIC development for each node
Solution Approach 2:
The patent applies parameter changes by leveraging variations in FPGA chip parameters across different technology nodes. The same FPGA architecture can be manufactured at different process nodes with corresponding performance and power characteristics, allowing system designers to select appropriate technology node parameters based on performance requirements without incurring prohibitive NRE costs for custom design at each node
3Device complexity
If using standardized commodity FPGA IC chips is performed to reduce NRE costs, then NRE costs and device accessibility are reduced, but performance and power efficiency compared to ASIC chips are degraded
Solution Approach 1:
The patent applies preliminary action by performing logic optimization and configuration during the field programming phase rather than during manufacturing. Configuration memory cells are programmed with optimized logic implementations that account for specific application requirements, allowing performance and power optimization to be achieved after manufacturing without incurring high NRE costs for custom ASIC design
Data Source
AI summary
A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.