Commodity FPGA Logic Drive Reduces ASIC NRE Costs
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Solution Overview
Problem
The high Non-Recurring Engineering (NRE) costs and complexity of designing and manufacturing Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips for advanced semiconductor technology nodes, such as those below 30 nm, hinder innovation and make it difficult for small companies to adopt new technologies, as the costs exceed $5 million to $100 million, and photo mask sets for 16 nm technology nodes can be over $2 million.
Innovation Solution
A standardized commodity logic drive is proposed, comprising multiple FPGA IC chips and non-volatile memory IC chips, which allows for field programming and reduces NRE costs by enabling developers to use advanced technology nodes with costs less than $10 million, similar to the 1990s semiconductor manufacturing foundry model, where innovators can implement innovations using standard commodity FPGA IC chips and write software in common programming languages like C, Java, or Python.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ASIC or COT chips are designed and manufactured for advanced semiconductor technology nodes, then performance and functionality are improved, but NRE costs and manufacturing complexity increase dramatically
Solution Approach 1:
The system segments the functionality into a reconfigurable logic array that can be dynamically programmed for different applications, rather than creating dedicated ASIC circuits for each application. This allows a single physical device to serve multiple application-specific purposes through software configuration.
Solution Approach 2:
The patent implements a dynamic reconfiguration capability where the logic device can change its functionality during operation or between operations through loading different configuration data. This dynamic adaptability replaces the static, application-specific nature of ASIC chips, allowing the same hardware to perform different functions as needed.
2Productivity
If ASIC or COT chips are designed for advanced technology nodes, then performance is improved, but NRE costs exceed $5 million to $100 million
Solution Approach 1:
Instead of creating expensive custom ASIC circuits for each application, the system uses a standardized logic device that can be programmed with different configuration data to replicate the functionality of various ASIC designs. This copying approach through software configuration eliminates the need for expensive custom manufacturing for each application.
Solution Approach 2:
The patent creates a universal logic device platform that can perform multiple application-specific functions through reconfiguration. This single universal device replaces the need for multiple specialized ASIC chips, dramatically reducing NRE costs while maintaining the ability to achieve high performance for different applications.
3Adaptability or versatility
If FPGA IC chips are used for a given application, then adaptability is improved, but semiconductor chip size increases, fabrication yield decreases, and fabrication cost increases
Solution Approach 1:
The system changes the operational parameters of a standardized logic device through software configuration rather than changing the physical hardware parameters. By modifying configuration data and control parameters, the device achieves different functionalities without requiring different physical chip designs, thereby maintaining consistent fabrication yield.
4Reliability
If ASIC or COT chip design is implemented for innovation, then application-specific optimization is improved, but the barrier to innovation increases due to high NRE costs
Solution Approach 1:
The patent enables innovators to independently configure and optimize logic devices for their specific applications using software tools and configuration data, without requiring access to expensive ASIC design and manufacturing services. This self-service capability allows small companies and individual innovators to achieve application-specific optimization at low cost.
Data Source
AI summary
A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.