Commodity FPGA Logic Drive With NVM for Lower NRE Scaling
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Solution Overview
Problem
The high Non-Recurring Engineering (NRE) costs and inefficiencies of transitioning from Field Programmable Gate Arrays (FPGA) to Application Specific IC (ASIC) chips for advanced semiconductor technology nodes hinder innovation and scalability in logic ASIC or COT IC chip designs, leading to increased power consumption and lower performance.
Innovation Solution
Implementing a standardized commodity logic drive using plural FPGA IC chips and non-volatile memory IC chips, which reduces NRE costs by allowing software development on existing FPGA technology, enabling efficient field programming for advanced applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transitioning from FPGA to ASIC chips for advanced semiconductor technology nodes, then performance and power efficiency are improved, but NRE costs and manufacturing complexity increase significantly
Solution Approach 1:
The patent segments the ASIC design process into modular IP blocks that can be independently developed, tested, and reused across multiple designs. This segmentation reduces the overall NRE cost and manufacturing complexity while maintaining the performance benefits of ASIC implementation at advanced technology nodes.
Solution Approach 2:
The patent utilizes parameter changes in semiconductor technology nodes (e.g., moving to 16nm, 14nm, or 10nm processes) to improve power efficiency and performance. By carefully selecting and adapting to specific process parameters, the design achieves better power efficiency without proportionally increasing manufacturing complexity.
2Adaptability or versatility
If using FPGA IC chips for advanced applications, then adaptability and ease of programming are maintained, but performance and power efficiency are lower compared to ASIC chips
Solution Approach 1:
The patent implements a dynamic design approach where the system can operate in different modes - fully programmable FPGA mode for maximum adaptability, or partially hardened ASIC mode for improved power efficiency. This dynamic flexibility allows optimization based on specific application requirements, balancing programming flexibility with power consumption.
Solution Approach 2:
The patent employs preliminary action by pre-configuring commonly used functional blocks and interfaces in the FPGA design before final deployment. This preliminary hardening of critical paths reduces power consumption while maintaining the ability to programmatically configure less critical functions, achieving a balance between adaptability and power efficiency.
3Productivity
If migrating to advanced semiconductor technology nodes below 30nm, then performance and power efficiency are improved, but NRE costs increase dramatically
Solution Approach 1:
The patent creates universal IP blocks and design modules that can be reused across multiple products and applications at advanced technology nodes. This universality amortizes the high NRE costs over multiple designs, making advanced node migration economically viable while achieving improved processing performance.
Solution Approach 2:
The patent uses copying by replicating and reusing proven design blocks and IP cores across different designs at advanced technology nodes. Instead of creating entirely new designs that would incur full NRE costs, the approach copies and adapts existing validated blocks, significantly reducing the effective NRE cost while maintaining high performance.
Data Source
AI summary
A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.