Multi-Chip FPGA Logic Drive for Lower NRE and ASIC Transition
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Solution Overview
Problem
The high cost and inefficiency of transitioning from Field Programmable Gate Array (FPGA) IC chips to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips due to larger size, higher power consumption, and increased Non-Recurring Engineering (NRE) costs, which hinders innovation and adoption of advanced semiconductor technology nodes.
Innovation Solution
A standardized commodity logic drive comprising multiple FPGA IC chips and non-volatile memory IC chips, allowing for field programming and reducing NRE costs by enabling software development without the need for expensive ASIC or COT chip design, thus facilitating innovation and adoption of advanced technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for a given application, then adaptability and ease of operation are improved, but semiconductor chip size increases, fabrication yield decreases, and fabrication cost increases
Solution Approach 1:
The invention divides the logic drive into multiple independent FPGA IC chips, each capable of being individually programmed and configured. This segmentation allows the system to maintain adaptability through software configuration while using smaller, more efficient chip physical dimensions, thereby resolving the contradiction between adaptability and chip size.
Solution Approach 2:
The logic drive is designed as a universal platform that can be programmed to perform multiple different logic functions through software configuration. This multi-functionality allows a single standardized hardware design to replace multiple specialized ASIC chips, reducing overall chip size requirements while maintaining adaptability across different applications.
2Adaptability or versatility
If FPGA IC chips are used for a given application, then adaptability is improved, but power consumption increases
Solution Approach 1:
The invention implements dynamic power management where the FPGA chips can be programmed and configured to activate only the necessary logic functions required for each specific application. This dynamic configuration allows the system to maintain adaptability while consuming only the power necessary for the active functions, rather than powering all possible functions continuously.
3Productivity
If ASIC or COT IC chips are used to replace FPGA, then performance is improved, but Non-Recurring Engineering (NRE) cost increases greatly
Solution Approach 1:
The invention uses software bitstreams to copy and load logic configurations into the FPGA chips, allowing the same logic design to be replicated across multiple chips without incurring additional NRE costs for each copy. This software-based copying mechanism enables high-performance multi-chip configurations while avoiding the prohibitive NRE costs associated with creating multiple ASIC mask sets.
Solution Approach 2:
The invention changes the parameter of logic configuration from fixed hardware (ASIC) to programmable software (FPGA bitstreams). This parameter change allows the system to achieve ASIC-level performance through optimized logic implementation while maintaining the flexibility and lower NRE costs of programmable devices, as the same hardware can be reconfigured for different applications without remanufacturing.
4Productivity
If advanced semiconductor technology nodes are adopted, then performance is improved, but NRE cost increases greatly
Solution Approach 1:
The invention segments the advanced technology benefits across multiple standardized FPGA chips rather than requiring a single complex ASIC at advanced nodes. This segmentation allows each chip to use optimized standard-cell libraries and proven manufacturing processes at advanced nodes, achieving high performance while avoiding the enormous NRE costs of custom ASIC development at those nodes.
Data Source
AI summary
A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.