Commodity FPGA Logic Drive With NVM to Cut ASIC NRE Cost
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Solution Overview
Problem
The current Field Programmable Gate Array (FPGA) IC chips have limitations such as larger size, lower yield, higher fabrication cost, higher power consumption, and lower performance compared to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips. Additionally, the high Non-Recurring Engineering (NRE) cost for designing ASIC or COT chips using advanced technology nodes slows down innovation and increases barriers for implementing new semiconductor technologies.
Innovation Solution
A standardized commodity logic drive is proposed, comprising plural FPGA IC chips and one or more non-volatile memory IC chips. This approach allows for field programming and user programming, enabling different applications requiring logic, computing, and processing functions. The logic drive is designed to reduce NRE costs and accelerate workload processing by using standardized commodity FPGA IC chips, similar to how commodity DRAM or flash memory IC chips are produced.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for logic functions, then adaptability and ease of operation are improved, but device size increases, manufacturing precision decreases, and fabrication cost increases
Solution Approach 1:
The system segments the logic function implementation into two parts: a standardized commodity FPGA chip that provides programmability and an ASIC controller that provides high-performance logic functions. This segmentation allows each component to be optimized for its specific function, resolving the contradiction between adaptability and manufacturing precision.
Solution Approach 2:
The invention creates a universal logic drive platform that can be programmed for different applications while maintaining high manufacturing precision through standardized production. The FPGA-based logic drive serves multiple functions across different applications, eliminating the need for custom ASIC design for each application.
2Adaptability or versatility
If FPGA IC chips are used for logic functions, then adaptability is improved, but power consumption increases and performance decreases
Solution Approach 1:
The system divides functionality between the FPGA logic drive (for adaptability) and the ASIC controller (for high-performance, low-power operations). This segmentation ensures that power-intensive operations are handled by the efficient ASIC while the FPGA handles only the necessary programmable logic functions.
Solution Approach 2:
The invention changes the operational parameters by using the FPGA in a standardized commodity configuration rather than a custom high-performance configuration, which reduces power consumption while maintaining sufficient adaptability for the application requirements.
3Power
If ASIC or COT chips are used for logic functions, then performance and power efficiency are improved, but NRE cost increases significantly
Solution Approach 1:
Instead of creating a custom ASIC for each application, the invention uses a standardized commodity FPGA chip that can be copied and programmed for different applications. This eliminates the high NRE costs associated with custom ASIC design while maintaining the ability to achieve high performance through programming.
Solution Approach 2:
The invention performs preliminary programming of the FPGA chip to configure it for specific applications before deployment. This preliminary action allows the standardized chip to be adapted to specific performance requirements without incurring the high NRE costs of custom ASIC design.
4Power
If advanced technology nodes are used for ASIC design, then performance is improved, but NRE cost increases greatly
Solution Approach 1:
The invention uses standardized commodity FPGA chips that are produced using advanced technology nodes through standardized manufacturing processes. This allows the benefits of advanced technology (high performance) to be achieved without the high NRE costs of custom ASIC design at those nodes.
Solution Approach 2:
The standardized FPGA chip serves as a universal platform that can be programmed for different applications requiring advanced technology performance. This universality eliminates the need for separate custom ASIC designs for each application, dramatically reducing NRE costs while maintaining access to advanced technology benefits.
Data Source
AI summary
A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.