Commodity FPGA Logic Drive With NVM for Lower NRE Costs

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Solution Overview

Problem

The high Non-Recurring Engineering (NRE) costs and inefficiencies of transitioning from Field Programmable Gate Arrays (FPGA) to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips, particularly in advanced semiconductor technology nodes, hinder innovation and scalability.

Innovation Solution

Utilizing a standardized commodity logic drive comprising plural FPGA IC chips and non-volatile memory IC chips, which reduces NRE costs by enabling field programming and allows for software development, similar to commodity DRAM or flash memory businesses, facilitating the use of advanced technology nodes without the high costs associated with ASIC or COT designs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If FPGA IC chips are used for a given application, then adaptability and ease of operation are improved, but semiconductor chip size increases, fabrication yield decreases, and fabrication cost increases compared to ASIC or COT chips

Engineering Contradiction:

ImproveadaptabilityVSAvoidfabrication cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The system is divided into two separate components: a standardized commodity FPGA IC chip that provides reconfigurable logic functionality, and a non-volatile memory IC chip that stores configuration data. This segmentation allows each component to be optimized independently - the FPGA chip can be smaller and more efficient while the memory chip handles the configuration storage, potentially improving overall fabrication efficiency and reducing costs compared to using a larger FPGA chip that must include its own configuration memory.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention creates a universal platform by using a standardized commodity FPGA IC chip that can be configured for different applications through software-loaded configuration data stored in a separate non-volatile memory IC chip. This multi-functional approach allows a single standardized chip design to serve multiple purposes, improving fabrication efficiency through standardization while maintaining the adaptability benefits of FPGA technology.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If FPGA IC chips are used for a given application, then adaptability is improved, but power consumption increases compared to ASIC or COT chips

Engineering Contradiction:

ImproveadaptabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The configuration data is pre-loaded into a non-volatile memory IC chip, which retains the configuration without power. When the system is powered on, the FPGA chip can quickly load its configuration from the memory chip without requiring continuous power for configuration storage. This preliminary action of pre-storing configuration data reduces the power consumption during operation compared to traditional FPGA implementations that require continuous power for configuration memory.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If advanced semiconductor technology nodes are used, then performance is improved, but Non-Recurring Engineering (NRE) costs increase greatly

Engineering Contradiction:

ImproveperformanceVSAvoidNRE cost

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system enables parameter changes by storing configuration data in a non-volatile memory IC chip that can be reprogrammed with different configuration sets. This allows the FPGA chip to be reconfigured for different applications by simply changing the configuration data in the memory chip, rather than requiring expensive mask sets for each application variant. This parameter change capability maintains high performance through advanced technology nodes while avoiding the high NRE costs associated with creating multiple ASIC variants.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12614012B2Logic drive based on standard commodity FPGA IC chips

Publication Date: 2026.04.28 ICOMETRUE CO LTD

AI summary

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.